Data Sheet

34 JN-DS-JN5142 1v0 © NXP Laboratories UK 2012
SPI
Master
MUX
UART0
DIO6/TXD0/JTAG_TDO/PWM2
DIO7/RXD0/JTAG_TDI/PWM3
DIO4/CTS0/JTAG_TCK/TIM0OUT
DIO5/RTS0/JTAG_TMS/PWM1/PC1
DIO17/COMP1M/SIF_D
Timer0
2-wire
Interface
SPICLK
DIO10/TIM0OUT/32KXTALOUT
SPIMOSI
SPIMISO
SPISEL0
DIO0/SPISEL1/ADC3
DIO3/RFTX/TIM0CAP
DIO2/RFRX/TIM0CK_GT
DIO1/SPISEL2/PC0/ADC4
DIO9/TIM0CAP/32KXTALIN
DIO8/TIM0CK_GT/PC1
DIO13/PWM3/ADE/RTS0/JTAG_TMS
DIO11/PWM1
DIO12/PWM2/ADO/CTS0/JTAG_TCK
DIO14/SIF_CLK/TXD0/JTAG_TD0/SPISEL1
DIO15/SIF_D/RXD0/JTAG_TDI/SPISEL2
DIO16/COMP1P/SIF_CLK
SPISEL1
SPISEL2
TXD0
RXD0
RTS0
CTS0
TIM0CK_GT
TIM0CAP
TIM0OUT
SIF_D
SIF_CLK
Pulse
Counters
PC0
PC1
JTAG
Debug
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TDO
Antenna
Diversity
ADO
ADE
PWMs
PWM1
PWM3
PWM2
Figure 22: DIO Block Diagram