User Manual

Jennic
JennicJennic
Jennic
© Jennic 2008 JN-DS-JN5139 v1.5 9
2 Pin Configurations
DIO6/TXD0
DIO7/RXD0
DIO4/CTS0
DIO5/RTS0
DIO19/TXD1
DIO20/RXD1
DIO17/CTS1/IP_SEL
DIO18/RTS1/IP_INT
VB_VCO
DIO10/TIM0OUT
SPIMISO
SPIMOSI
SPISEL0
DIO0/SPISEL1
DIO3/SPISEL4/RFTX
DIO2/SPISEL3/RFRX
DIO1/SPISEL2
DIO9/TIM0CAP/CLK32K
DIO8/TIM0CK_GT
DIO13/TIM1OUT
DIO11/TIM1CK_GT
DIO12/TIM1CAP
DIO14/SIF_CLK/IP_CLK
DIO15/SIF_D/IP_DO
DIO16/IP_DI 1
2
3
4
5
VSS2
RESETN
VSS3
VSSS
6
7
8
9
10
11
12
13
14
XTALOUT
XTALIN
VB_SYN
VCOTUNE
VB_DIG2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
29
30
31
32
33
34
35
36
37
38
39
40
41
42
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD1
COMP1M
COMP1P
IBIAS
RFP
VB_RF
RFM
VREF
ADC1
ADC2
ADC3
ADC4
VB_A
DAC1
DAC2
COMP2P
COMP2M
SPICLK
VB_DIG1
VSS1
VB_MEM
VDD2
PADDLE
Figure 2: 56-pin QFN Configuration (top view)
Note: Please refer to Appendix B.3.11 for important applications
information regarding the connection of the PADDLE to the PCB.