User Manual

Jennic
JennicJennic
Jennic
8 JN-DS-JN5139 v1.5 © Jennic 2008
1.5 Block Diagram
32-bit RISC CPU
RAM
96kB
ROM
192kB
Reset
SPI
M
U
X
UART0
UART1
32kHz
Osc
WT1
WT0
Wakeup
Security
Coprocessor
DIO6/TXD0
DIO7/RXD0
DIO4/CTS0
DIO5/RTS0
DIO19/TXD1
DIO20/RXD1
DIO17/CTS1/IP_SEL
DIO18/RTS1/IP_INT
Baseband
Controller
Modem
Radio
Programmable
Interrupt
Controller
Timer0
2-Wire
Serial
Interface
Timer1
DAC1
DAC2
ADC
Comparator2
SPICLK
DIO10/TIM0OUT
SPIMOSI
SPIMISO
SPISEL0
DIO0/SPISEL1
DIO3/SPISEL4/RFTX
DIO2/SPISEL3/RFRX
DIO1/SPISEL2
DIO9/TIM0CAP/CLK32K
DIO8/TIM0CK_GT
DIO13/TIM1OUT
DIO11/TIM1CK_GT
DIO12/TIM1CAP
DIO14/SIF_CLK/IP_CLK
DIO15/SIF_D/IP_DO
DIO16/IP_DI
From Peripherals
M
U
X
RESETN
Wireless
Transceiver
ADC4
ADC1
ADC2
ADC3
DAC1
DAC2
COMP2P
COMP2M
Clock
Generator
XTALIN
XTALOUT
RFM
RFP
VCOTUNE
Tick Timer
Voltage
Regulators
1.8V
Temperature
Sensor
Supply
Monitor
VDD1
VDD2
Intelligent
Peripheral
IBIAS
VB_xx
OTP
eFuse
48-byte
Comparator1
COMP1P
COMP1M
Figure 1: JN5139 Block Diagram