User Manual

Jennic
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Jennic
54 JN-DS-JN5139 v1.5 © Jennic 2008
17.3.3 Two-wire serial interface
t
BUF
t
LOW
t
HD;STA
t
F
t
R
t
HIGH
t
SU;DAT
t
SU;STA
t
HD;STA
t
SU;STO
t
R
t
F
SIF_D
SIF_CLK
Figure 43: Two-wire serial Interface Timing
Standard Mode Fast Mode
Parameter Symbol
Min Max Min Max
Unit
SIF_CLK clock frequency
f
SCL
0 100 0 400 kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
t
HD:STA
4 - 0.6 - µs
LOW period of the SIF_CLK clock
t
LOW
4.7 - 1.3 - µs
HIGH period of the SIF_CLK clock
t
HIGH
4 - 0.6 - µs
Set-up time for repeated START condition t
SU:STA
2 - 0.5 - µs
Data setup time SIF_D t
SU:DAT
0.25 - 0.1 - µs
Rise Time SIF_D and SIF_CLK t
R
- 1000 20+0.1Cb 300 ns
Fall Time SIF_D and SIF_CLK t
F
- 300 20+0.1Cb 300 ns
Set-up time for STOP condition t
SU:STO
4 - 0.6 - µs
Bus free time between a STOP and START
condition
t
BUF
4.7 - 1.3 - µs
Capacitive load for each bus line C
b
- 400 - 400 pF
Noise margin at the LOW level for each
connected device (including hysteresis)
V
nl
0.1VDD - 0.1VDD - V
Noise margin at the HIGH level for each
connected device (including hysteresis)
V
nh
0.2VDD - 0.2VDD - V
17.3.4 Power Down and Wake-Up timings
Parameter Min Typ Max Unit Notes
Wake up from Deep Sleep
(or reset)
2.5 + 0.5* program
size in kBytes
ms Assumes SPI clock to
external Flash is16MHz
Wake up from Sleep
(memory not held)
2.5 + 0.5* program
size in kBytes
ms Assumes SPI clock to
external Flash is16MHz
Wake up from Sleep
(Memory held)
2.5 ms
Wake up from CPU Doze
mode
0.2 µs
Note: The 2.5ms time is from release of reset wakeup event to the CPU executing code. At this point if the Flash is
read there is an additional startup delay, as shown in the table.