User Manual

Jennic
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© Jennic 2008 JN-DS-JN5139 v1.5 53
Parameter Min Typ Max Unit Notes
External Reset pulse width
(t
RST
)
1
µs
Assumes internal pullup
resistor value of 100K
worst case and ~5pF
external capacitance
External Reset threshold
voltage (V
RST
)
VDD2 x 0.7 V Minimum voltage to
avoid being reset
Internal Power-on Reset
threshold voltage (V
POT
)
1.90
1.95
2.00
V VDD2 = 2.2V
VDD2 = 3.0V
VDD2 = 3.6V
Note 1
Reset rise time (t
RISE
) 1 ms
Reset stabilisation time
(t
STAB
)
2.5 ms Note 2
1
VDD rise time of 1ms.
2
Time from release of reset to start of executing ROM code. Loading program from Flash occurs in addition to this.
17.3.2 SPI Timing
t
SSH
t
SSS
t
CK
t
SI
t
HI
MOSI
(mode=1,3)
SS
MOSI
(mode=0,2)
MISO
(mode=0,2)
MISO
(mode=1,3)
t
VO
t
VO
CLK
(mode=0,1)
t
SI
t
HI
CLK
(mode=2,3)
Figure 42: SPI Timing (Master)
Parameter Symbol Min Max Unit
Clock period t
CK
62.5 - ns
Data setup time t
SI
15.3 @ 2.7-3.6V
30.5 @ 2.2-3.6V
- ns
Data hold time t
HI
0 ns
Data invalid period t
VO
- 15 ns
Select set-up period t
SSS
60 - ns
Select hold period t
SSH
30 (SPICLK = 16MHz)
0 (SPICLK<16MHz, mode=0 or 2)
60 (SPICLK<16MHz, mode=1 or 3)
- ns