User Manual

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44 JN-DS-JN5139 v1.5 © Jennic 2008
14.1 Connecting Devices
The clock and data lines, SIF_D and SIF_CLK, are alternate functions of DIO lines 15 and 14 respectively. The serial
interface function of these pins is selected when the interface is enabled. They are both bi-directional lines,
connected internally to the positive supply voltage via weak (45k Ω ) programmable pull-up resistors. However, it is
recommended that external 4.7k Ω pull-ups be used for reliable operation at high bus speeds, as shown in Figure 36.
When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-
drain or open-collector in order to perform the wired-AND function. The number of devices connected to the bus is
solely dependent on the bus capacitance limit of 400pF.
SIF_CLK
SIF_D
Vdd
D1_OUT
D1_IN
CLK1_IN
CLK1_OUT
D2_IN
CLK2_IN
CLK2_OUT
DEVICE 1
DEVICE 2
R
P
R
P
Pullup
Resistors
D2_OUT
JN5139
SIF
55
56
Figure 36: Connection Details
14.2 Clock Stretching
Slave devices can use clock stretching to slow down the transfer bit rate. After the master has driven SIF_CLK low,
the slave can drive SIF_CLK low for the required period and then release it. If the slave’s SIF_CLK low period is
greater than the master’s low period the resulting SIF_CLK bus signal low period is stretched thus inserting wait
states.
SIF_CLK
SIF_CLK
SIF_CLK
Master SIF_CLK
Slave SIF_CLK
Wired-AND SIF_CLK
Clock held low
by Slave
Figure 38: Clock Stretching