User Manual

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© Jennic 2008 JN-DS-JN5139 v1.5 43
14 Two-Wire Serial interface
The JN5139 includes an industry standard two-wire synchronous serial interface (SIF) that provides a simple and
efficient method of data exchange between devices. The system uses a serial data line (SIF_D) and a serial clock
line (SIF_CLK) to perform bi-directional data transfers and includes the following features:
• Compatible with both I
2
C and SMbus peripherals (master only mode)
• Software programmable clock frequency
• Clock stretching and wait state generation
• Software programmable acknowledge bit
• Interrupt or bit-polling driven byte-by-byte data-transfers
• Bus busy detection
• Support for 7 and 10 bit addressing modes
Prescale
Register
Receive
Register
Command
Register
Status
Register
Transmit
Register
Byte
Command
Controller
Data I/O
Shift
Register
Bit
Command
Controller
Clock
Generator
SIF_CLK
SIF_D
Processor Bus
Figure 35: SIF Block Diagram
The prescale register allows the interface to be configured to operate at up to 400kbit/s. The clock generator handles
the clock stretching required by some slave devices.
The Byte Command Controller handles traffic at the byte level. It takes data from the Command Register and
translates it into sequences based on the transmission of a single byte. By setting the start, stop, read, write and
acknowledge control bits in the command register it is possible to generate read or write sequences on the bus.
The data I/O shift register contains the data associated with the current transfer. During a read operation, data is
shifted into this register from the SIF_D line. When the read is complete the byte is copied into the receive register
and can be accessed.
During a write operation the contents of the transmit register are copied into the shift register and then onto the SIF_D
line. It is possible to generate an interrupt upon the completion of a byte transmission or reception. If interrupt-driven
communication is not desired it is possible to poll the status of the interface.
The first byte of data transferred by the device after a start bit is the slave address. The JN5139 supports both 7-bit
and 10-bit slave addresses by generating either one or two address transfers. Only the slave with a matching
address will respond by returning an acknowledge bit.