User Manual

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42 JN-DS-JN5139 v1.5 © Jennic 2008
value of the generated RTS (negated if the receive FIFO fill level is 15 and another character starts to be received,
and asserted when the receive FIFO is read), and only transmits data when the incoming CTS is asserted.
Characters are read one byte at a time from the Receive FIFO and are written to the Transmit FIFO. The Transmit
and Receive FIFOs can be cleared and reset independently of each other. The status of the transmitter can be
checked to see if it is empty, and if there is a character being transmitted. The status of the receiver can also be
checked, indicating if conditions such as parity error, framing error or break indication have occurred. It also shows if
an overrun error occurred (receive buffer full and another character arrives) and if there is data held in the receive
FIFO.
UART 0 signals CTS, RTS, TXD and RXD are alternate functions of pins DIO4, 5, 6 and 7 respectively and UART 1
signals CTS, RTS, TXD and RXD are alternate functions of pins DIO17, 18, 19 and 20 respectively. If CTS and RTS
are not required on the devices external pins, then they may be disabled, this allows the alternate DIOx to be used
instead.
Note: The hardware flow control within the UART block negates RTS when the receive FIFO is about to become full,
this occurs when the UART has started receiving the last byte that it can accept. In some instances it has been
observed that remote devices that are transmitting data do not respond quickly enough to the de-asserted CTS and
continue to transmit data. In these instances the data will be lost in a receive FIFO overflow.
13.1 Interrupts
Interrupt generation can be controlled for the UART block, and is divided into four categories:
• Received Data Available: Is set when data in the Rx FIFO queue reaches a particular level (the trigger level can
be configured as 1, 4, 8 or 14) or if no character has been received for 4 character times.
• Transmit FIFO Empty: set when the last character from the Tx FIFO is read and starts to be transmitted.
• Receiver Line Status: set when one of the following occur (1) Parity Error - the character at the head of the
receive FIFO has been received with a parity error, (2) Overrun Error - the Rx FIFO is full and another character
has been received at the Receiver shift register, (3) Framing Error - the character at the head of the receive
FIFO does not have a valid stop bit and (4) Break Interrupt – occurs when the RxD line has been held low for an
entire character.
• Modem Status: Generated when the CTS (Clear To Send) input control line changes.
13.2 UART Application
The following example shows the UART connected to a 9-pin connector compatible with a PC. The software
developer kit uses such an interface as the debugger interface between the JN5139 and a PC. As the JN5139
device pins do not provide the RS232 line voltage a level shifter is used.
JN5139
RTS
CTS
TXD
RXD
UART0
RS232
Level
Shifter
1
2
3
4
5
6
7
8
9
CD
RD
TD
DTR
SG
DSR
RTS
CTS
RI
PC COM Port
Pin Signal 1 5
6 9
46
47
45
44
Figure 34 JN5139 Serial Communication Link