User Manual

Jennic
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38 JN-DS-JN5139 v1.5 © Jennic 2008
Timer 1 is configured to count the rising edge events on the clk/gate pin over a constant period. This converts the
tacho pulse stream output into a count proportional to the motor speed. This value is then used by the application
software executing the control algorithm.
JN5139
Timer 0
Timer 1
CLK/GATE
CLK/GATE
CAPTURE
CAPTURE
PWM
PWM
M
Tacho
48
50
52
53
54
1N4007
+12V
IRF521
51
1 pulse/rev
Figure 31: Closed Loop PWM Speed Control Using JN5139 Timers