User Manual

Jennic
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Jennic
© Jennic 2008 JN-DS-JN5139 v1.5 35
12 Timers
12.1 Peripheral Timer / Counters
Two general-purpose timer / counter units are available that can be independently configured to operate in one of five
modes. The timers have the following features:
• 16-bit prescaler, divides system clock by 2
prescale
value as the clock to the timer
• Clocked from internal system clock
• 16-bit counter, 16-bit Rise and Fall (period) registers
• Timer: can generate interrupts off Rise and Fall counts. Can be gated by external signal
• Counter: counts number of transitions on external event signal. Can use low-high, high-low or both
transitions
• PWM/Single pulse: outputs repeating Pulse Width Modulation signal or a single pulse. Can set period and
mark-space ratio
• Capture: measures times between transitions of an applied signal.
• Delta-Sigma: Return-To-Zero (RTZ) and Non-Return-to-Zero (NRZ) modes
Interrupt
Generator
Rise
Fall
Delta-Sigma
Counter
Reset Generator
=
Prescaler
INT
Int Enable
Sys Clk
S/w
Reset
System
Reset
Single
Shot
=
S
R
OE
Gate
Gate
Edge
Select
Reset
PWM/Delta-
Sigma
Capture
Generator
Capture
Enable
PWM/∆−Σ
PWM/∆−Σ
TIMxCK_GT
TIMxOUT
TIMxCAP
Figure 26: Timer Unit Block Diagram
The clock source for the timer unit is fed from the 16MHz system clock. This clock passes to a 16-bit prescaler where
a value of 0 leaves the clock unmodified and other values divide it by 2
prescale
value. For example, a prescale value
of 2 applied to the 16MHz system clock source results in a timer clock of 4MHz. The value of the prescaler is set
through software.