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11 Intelligent Peripheral Interface

The Intelligent Peripheral (IP) Interface is provided for systems that are more complex, where there is a processor

that requires a wireless peripheral. As an example, the JN5139 may provide a complete IEEE802.15.4, ZigBee or

other wireless network to a phone, computer, PDA, set-top box or games console. No resources are required from

the main processor compared to a transceiver as the complete wireless protocol may be run on the internal JN5139

CPU. The wireless peripheral may be controlled via one of the UARTs but the IP interface is intended to provide a

high-speed, low-processor-overhead interface.

The intelligent peripheral interface is a SPI slave interface and uses pins shared with other DIO signals. The

interface is designed to allow message passing and data transfer. Data received and transmitted on the IP interface

is copied directly to and from a dedicated area of memory without intervention from the CPU. This memory area, the

intelligent peripheral memory block, contains 64 32-bit word receive and transmit buffers.

JN5139

Intelligent

Peripheral

Interface

SPI

MASTER

System Processor

(e.g. in cellphone, computer)

CPU

IP_DO SPIMISO

IP_INT SPIINT

IP_DI SPIMOSI

SPISEL

IP_SEL

IP_CLK SPICLK

Figure 24: Intelligent Peripheral Connection

The interface functions as a SPI slave. It is possible to select the clock edge of IP_CLK on which data on the IP_DIN

line of the interface is sampled, and the state of data output IP_DOUT is changed. The order of transmission is MSB

first. The IP_DO data output is tri-stated when the device is inactive, i.e. the device is not selected via IP_SEL. An

interrupt output line IP_INT is available so that the JN5139 can indicate to an external master that it has data to

transfer.

The IP interface signals IP_CLK, IP_DO, IP_DI, IP_SEL, IP_INT are alternate functions of pins DIO14 to 18

respectively.

11.1 Data Transfer Format

Transfers are started by the remote processor asserting the IP_SEL line and terminated by the remote processor de-

asserting IP_SEL.

Data transfers are bi-directional and traffic in both directions has a format of status byte, data length byte (of the

number of 32-bit words to transfer) and data packet (from the receive and transmit buffers). The first byte transferred

in either direction is a status byte with the following format:

Bit Field Description

7:2 RSVD Reserved, set to 0.

1 TXQ 1: Data queued for transmission

0 RXRDY 1: Buffer ready to receive data

Table 4: IP Status Byte Format

If data is queued for transmission and the recipient has indicated that they are ready for it (RXRDY in incoming status

byte was 1), the next byte to be transmitted is the data length in words. If either the JN5139 or the remote processor