User Manual

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30 JN-DS-JN5139 v1.5 © Jennic 2008
10 Serial Peripheral Interface
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN5139 and
peripheral devices. The JN5139 operates as a master on the SPI bus and all other devices connected to the SPI are
expected to be slave devices under the control of the JN5139 CPU. The SPI includes the following features:
• Full-duplex, three-wire synchronous data transfer
• Programmable bit rates up to 16Mbps
• Programmable transaction size of 8,16 or 32 bits
• Supports standard SPI modes 0, 1, 2, 3 to allow control over the relationship between clock and transmit /
receive data
• Automatic slave select generation (up to 5 slaves)
• Maskable transaction complete interrupt
• LSB First or MSB First Data Transfer
Clock
Divider
SPI Bus
Cycle
Controller
Data Buffer
31 15 7
DIV Clock Edge Select Data CHAR_LEN LSB
SPIMISO
SPIMOSI
SPICLK
Select
Latch
SPISEL [4..0]
16 MHz
0
Figure 22: SPI Block Diagram
The SPI bus employs a simple shift register data transfer scheme. Data is clocked out of and into the active devices
in a first-in, first-out fashion allowing SPI devices to transmit and receive data simultaneously.
There are three dedicated pins SPICLK, SPIMOSI, SPIMISO that are shared across all devices on the bus. Master-
Out-Slave-In or Master-In-Slave-Out data transfer is relative to the clock signal SPICLK generated by the JN5139.
The JN5139 provides five slave selects, SPISEL0 to SPISEL4 to allow five SPI peripherals on the bus. SPISEL0 is a
dedicated pin and SPISEL1 to 4, are alternate functions of pins DIO0 to 3 respectively. This allows a serial flash
memory to be connected to SPISEL0 and download to internal RAM via software from reset.
The interface can transfer 8, 16 or 32 bits without software intervention and can keep the slave select lines asserted
between transfers when required, to enable longer transfers to be performed.