User Manual

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7 Interrupt System

The interrupt system on the JN5139 is a hardware-vectored interrupt system. The JN5139 provides several interrupt

sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the

device. When an interrupt occurs the CPU stops executing the current program and loads its program counter with a

fixed hardware address specific to that interrupt. The interrupt handler or interrupt service routine is stored at this

location and is run on the next CPU cycle. Execution of interrupt service routines is always performed in supervisor

mode. Interrupt sources and their vector locations are listed in Table 2 below:

Interrupt Source Vector Location Interrupt Definition

Reset 0x100 Software or hardware reset

Bus Error 0x200 Bus error or attempt to access invalid physical address

Tick Timer 0x500 Tick Timer expiry

Alignment 0x600 Load/Store to naturally not aligned location

Illegal Instruction 0x700 Illegal instruction in instruction stream

Hardware Interrupts 0x800 Hardware Interrupt

System Call 0xC00 System Call Initiated by software (l.sys instruction)

Trap 0xE00 Caused by l.trap instruction

Table 2: Interrupt Vectors

7.1 System Calls

Executing the l.sys instruction causes a system call interrupt to be generated. The purpose of this interrupt is to

allow a task to switch into supervisor mode when a real time operating system is in use, see section 3 for further

details. It also allows a software interrupt to be issued, as does execution of the l.trap instruction.

7.2 Processor Exceptions

7.2.1 Bus Error

A bus error exception is generated when software attempts to access a memory address that does not exist, or is not

populated with memory or peripheral registers.

7.2.2 Alignment

Alignment exceptions are generated when software attempts to access objects that are not aligned to natural word

boundaries. 16-bit objects must be stored on even byte boundaries, while 32-bit objects must be stored on quad byte

boundaries. For instance, attempting to read a 16-bit object from address 0xFFF1 will trigger an alignment exception

as will a read of a 32-bit object from 0xFFF1, 0xFFF2 or 0xFFF3. Examples of legal 32-bit object addresses are

0xFFF0, 0xFFF4, 0xFFF8 etc.

7.2.3 Illegal Instruction

If the CPU reads an unrecognised instruction from memory as part of its instruction fetch, it will cause an illegal

instruction exception.