User Manual

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6 Reset

A system reset initialises the device to a predefined state and forces the CPU to start program execution from the

reset vector. The reset process that the JN5139 goes through is as follows.

When power is applied, the 32kHz oscillator starts up and stabilises, which takes approximately 100µsec. At this

point, the 16MHz crystal oscillator is enabled and power is applied to the processor and digital logic. The logic blocks

are held in reset until the 16MHz crystal oscillator stabilises, which typically takes 2.5ms.

Once the oscillator is up and running the internal reset is removed from the CPU and peripheral logic and the CPU

starts to run code beginning at the reset vector, consisting of initialisation code and then optionally the resident Boot

Loader (described in JN-AN-1003 Boot Loader Operation [2]).

Section 17.3.1 provides detailed electrical data and timing.

The JN5139 has three sources of reset:

• Internal Power-on Reset

• External Reset

• Software Reset

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Note: When the device exits a reset condition, device operating

parameters (voltage, frequency, temperature, etc.) must be met to ensure

operation. If these conditions are not met, then the device must be held in

reset until the operating conditions are met. (See section 17.3.1)

6.1 Internal Power-on Reset

For the majority of applications the internal power-on reset is capable of generating the required reset signal. When

power is applied to the device, the power-on reset circuit monitors the rise of the VDD supply. When VDD reaches

the specified threshold, the reset signal is generated and can be observed as a rising edge on the RESETN pin. This

signal is held internally until the power supply and oscillator stabilisation time has elapsed, at which point the internal

reset signal is then removed and the CPU is allowed to run.

RESETN Pin

Internal RESET

VDD

Figure 10: Internal Power-on Reset

If the application requires a power supply reset to be used, i.e. removing and then applying VDD, it is important that

the device decoupling capacitors are completely discharged before the VDD is re-applied. Failure to do so may inhibit