User Manual

Jennic
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Jennic
12 JN-DS-JN5139 v1.5 © Jennic 2008
VDD1
Analogue
I/O Pin
VSSA
Analogue
Peripheral
Figure 3 Analogue I/O Cell
2.2.6 Digital Input/Output
Digital I/O pins on the JN5139 can have signals applied up to 2V higher than VDD2 (with the exception of pins DIO9
and DIO10 that are 3V tolerant) and are therefore TTL-compatible with VDD2 > 3V. For other DC properties of these
pins see section 17.2.3 I/O Characteristics.
When used in their primary function all Digital Input/Output pins are bi-directional and are connected to weak internal
pull up resistors (40kΩ nominal) that can be disabled. When used in their secondary function (selected when the
appropriate peripheral block is enabled) then their direction is fixed by the function. The pull up resistor is enabled or
disabled independently of the function and direction.
A schematic view of the digital I/O cell is in Figure 4: DIO Pin Equivalent Schematic.
I
O
IE
VDD2
VSS
Pu
R
PU
R
PROT
OE
DIO[x] Pin
Figure 4: DIO Pin Equivalent Schematic
Each DIO pin configuration is programmed through software library calls. The configuration includes the direction of
each pin, input or output. When a peripheral that uses the cell as part of its I/O is enabled, then the pin state will be
automatically configured by the peripheral. The use of the pull-up resistor Rpu for each pin can be configured, the
default state from reset is enabled.
In reset, the digital peripherals are all off and the DIO pins are set as high-impedance inputs. During sleep and deep
sleep, the DIO pins retain both their input/output state and output level that was set as sleep commences. If the DIO
pins were enabled as inputs and the interrupts were enabled these pins may be used to wake up the JN5139 from
sleep.