User Manual

Jennic
JennicJennic
Jennic
© Jennic 2008 JN-DS-JN5139 v1.5 75
B.3 Applications Information
B.3.1 Typical Application Schematic
43
CTS1
VB_DIG2
1
RTS1
TXD1
RXD1
VSS2
RESETN
VSSS
XTALOUT
I/O Line
XTALIN
VB_SYN
VB_DIG1
ADC2
RFP
VB_RF
RFM
VREF
ADC1
ADC4
VB_A
DAC1
29
15
ADC3
VSS3
IBIAS
MOSI
SPISEL0
SPISEL1
VSS1
VB_MEM
SPISEL2
SPISEL3
VCOTUNE
MISO
VB_VCO
VDD1
COMP1M
COMP1P
DAC2
COMP2P
COMP2M
SPICLK
TIM0CK_GT
VDD2
TIM1CK_GT
TIM1CAP
TIM1OUT SIF_CLK
SIF_D
SPISEL4
CTS0
RTS0
TXD0
RXD0
TIM0OUT
TIM0CAP
Jennic
IC1: JN5139
Vcc
UART 0
Timers
8
7
6
5
1
2
3
4
Vcc
Vcc
UART 1
RESET
Two Wire
Serial Port
SPI Selects
Analogue IO
SS
SDO
WP
Vss
Vcc
HOLD
CLK
SDI
Printed Antenna
C2
C9
C8
R4
R9
C3
C1
C4
C5
C6
C15
C11
C10
C7
Y1
C12
C13
IC2
Serial
Flash
Memory
Vcc
PADDLE
NOTES:
1) VB_SYN and VB_REF should have an
additional 47pF capacitor to ground.
2) A 10uF tantalum capacitor is reuiired
between VCC and ground.
Figure 50: Application Schematic
Table 6: Bill of Materials
Components Values
C1, C2, C3, C4, C5, C6, C7, C12, C13, C15 100nF
C10, C11 15pF (COG)
C9 3n3F
C8 330pF (COG)
R4
4k7 Ω
R9
43k Ω
Y1 TSX-10A 16MHz Crystal TN4-25820
IC1 JN5139
IC2 128kB Serial Flash