User Manual

Jennic

JennicJennic

Jennic

Because this sensor is on-chip, any measurements taken must account for the thermal time constants. For example

if the device recently came out of sleep mode the user application should wait until the temperature has stabilized

before taking a measurement.

15.2 Digital to Analogue Converter

The Digital to Analogue Converter (DAC) provides two output channels and is capable of producing voltages of 0 to

Vref or 0 to 2Vref where Vref is selected between the internal reference and the VREF pin, with a resolution of 11 bits

and a minimum conversion time of 9

secs (2MHz clock).

15.2.1 Operation

The output range of each DAC can be set independently to swing between 0V to either the reference voltage or twice

the reference voltage. The reference voltage is selected from the internal reference or the VREF pin. For example,

an external reference of 0.8V supplied to VREF may be used to set DAC1 maximum output of 0.8V and DAC2

maximum output of 1.6V.

The DAC output amplifier is capable of driving a capacitive load up to that specified in section 17.3.9.

Programmable clock periods allow a trade-off between conversion speed and resolution. The full 11-bit resolution is

achieved with the 250kHz clock rate. See section 17.3.8, electrical characteristics, for more details.

The conversion period of the DACs are given by the same formula as the ADC conversion time and so can vary

between 9 and 120uS. The DAC values may be updated at the same time as the ADC is active.

The clock divider ratio, interrupt enable and reference voltage select are all controlled through software, options

common to both the ADC and DAC. The DAC output range and initial value can be set and the subsequent updates

provided by updating only the DAC value. Polling is available to determine if a DAC channel is busy performing a

conversion. The DAC can be disabled which will power down the DAC cell.

Simultaneous conversions with DAC1 and DAC2 is not possible. To use both DACs at the same time it is necessary

to interleave the conversions. This is achieved by firstly setting the DAC1 and DAC2 retain bits, which holds the DAC

outputs stable. Conversion on either channel can then be performed by disabling the unused channel and enabling

the channel to be updated.

15.3 Comparators

The JN5139 contains two analogue comparators COMP1 and COMP2 that are designed to have true rail-to-rail

inputs and operate over the full voltage range of the analogue supply VDD1. The hysteresis level (common to both

comparators) can be set to a nominal value of 0mV, 10mV, 20mV or 40mV. In addition, the source of the negative

input signal for each comparator (COMP1M and COMP2M) can be set to one of the internal voltage reference, the

output of DAC1 or DAC2 (COMP1 or COMP2 respectively) or the external pin. The comparator outputs are routed to

internal registers and can be polled, or can be used to generate interrupts. The comparators can be disabled to

reduce power consumption.

The comparators have a low power mode where the response time of the comparator is slower than normal and is

specified in section 17.3.10. This mode may be used during non-sleep operation however it is particularly useful in

sleep mode to wake up the JN5139 from sleep where low current consumption is important. The wakeup action and

the configuration for which edge of the comparator output will be active are controlled through software. In sleep

mode the negative input signal source defaults to the external pins.