User Manual

Jennic
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Jennic
36 JN-DS-JN5139 v1.5 © Jennic 2008
The counter is optionally gated by a signal on the clock / gate input (TIMxCK_GT). If the gate function is selected the
counter is frozen when the clock/gate input is high.
An interrupt can be generated when the counter is equal to the value in either of the High or Low registers.
The internal Output Enable (OE) signal enables or disables the timer output.
The Timer 0 signals CK_GT, CAP and OUT are alternate functions of pins DIO8, 9 and 10 respectively and Timer 1
signals CK_GT, CAP and OUT are alternate functions of pins DIO11, 12, and 13 respectively. Selection of either the
Timer or DIOx functionality is made through software, in either case the timer still functions internally.
12.1.1 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode allows the user to specify an overall cycle time and pulse length within the
cycle. The pulse can be generated either as a single shot or as a train of pulses with a repetition rate determined by
the cycle time.
In this mode, the cycletime and low periods of the PWM output signal can be set by the values of two independent
16-bit registers (Fall and Rise). The counter increments and its output is compared to the 16-bit Rise and Fall
registers. When the counter is equal to the Rise register, the PWM output is set to high; when the counter reaches
the Fall value, the output returns to low. In continuous mode, when the counter reaches the Fall value, it will reset
and the cycle repeats. The PWM waveform is available on TIMxOUT when the output driver is enabled.
Rise
Fall
Figure 27: PWM Output Timings
12.1.2 Capture Mode
The capture mode can be used to measure the time between transitions of a signal applied to the capture input
(TIMxCAP). When the capture is started, on the next low-to-high transition of the captured signal, the count value is
stored in the Rise register, and on the following high-to-low transition, the counter value is stored in the Fall register.
The pulse width is the difference in counts in the two registers multiplied by the driving clock (in all cases this must be
the 16MHz clock and so the prescaler must be set to 0). Upon reading the capture registers the counter is stopped.
The values in the High and Low registers will be updated whenever there is a corresponding transition on the capture
input, and the value stored will be relative to when the mode was started. Therefore, if multiple pulses are seen on
TIMxCAP before the counter is stopped only the last pulse width will be stored.
CLK
CAPT
x
9
3
x 14
t
RISE
t
RISE
t
F
A
L L
t
FALL
Rise
Fall
9
5 43
7
Capture Mode Enabled
Figure 28: Capture Mode