User Manual
Jennic
JennicJennic
Jennic
© Jennic 2008 JN-DS-JN5139 v1.5 31
SI
SO
C
SS
Slave 0
Flash
Memory
JN5139
37
38
41
42
43
36
33
34
SI
SO
C
SS
Slave 1
User
Defined
SI
SO
C
SS
Slave 2
User
Defined
SI
SO
C
SS
Slave 3
User
Defined
SI
SO
C
SS
Slave 4
User
Defined
SPIMISO
SPIMOSI
SPICLK
SPISEL4
SPISEL2
SPISEL3
SPISEL1
SPISEL0
Figure 23: Typical JN5139 SPI Peripheral Connection
The data transfer rate on the SPI bus is determined by the SPICLK signal. The JN5139 supports transfers at
selectable data rates from 16MHz to 250kHz selected by a clock divider. Both SPICLK clock phase and polarity are
configurable. The clock polarity controls if SCLK is high or low between transfers (and hence the polarity of the first
clock edge in a transfer). The clock phase and polarity determines which edge of SPICLK is used by the JN5139 to
present new data on the SPIMOSI line; the opposite edge will be used to read data from the SPIMISO line.
SPICLK
Polarity Phase
Mode Description
0
0 0 SPICLK is low when idle – the first edge is positive.
Valid data is output on SPIMOSI before the first clock and changes every
negative edge. SPIMISO is sampled every positive edge.
0
1 1 SPICLK is low when idle – the first edge is positive.
Valid data is output on SPIMOSI every positive edge. SPIMISO is sampled every
negative edge.
1
0 2 SPICLK is high when idle – the first edge is negative.
Valid data is output on SPIMOSI before the first clock edge and is changed
every positive edge. SPIMISO is sampled every negative edge.
1
1 3 SPICLK is high when idle – the first edge is negative.
Valid data is output on SPIMOSI every negative edge. SPIMISO is sampled
every positive edge.
Table 3 SPI Configurations
If more than one SPISEL line is to be used in a system they must be used in numerical order, for instance if 3 SPI
select lines are to be used, they must be SPISEL0, 1 and 2. A SPISEL line can be configured to automatically
deassert between transactions if required, or it may stay asserted over a number of transactions. For devices such
as memories where a large amount of data can be received by the master by continually providing SPICLK
transitions, the ability for the select line to stay asserted is an advantage since it keeps the slave enabled over the
whole of the transfer.