Datasheet

NTE74LS76A
Integrated Circuit
TTL − Dual J−K Flip−Flop with Preset and Clear
Description:
The NTE74LS76A is a dual J−K flip−flop in a 16−Lead plastic DIP type package that contains
two independent negative−edge−triggered flip−flops. The J and K inputs must be stable one set-
up time prior to the high−to−low clock transitions for predictable operation. The preset and clear
are asynchronous active low inputs. When low they override the clock and data inputs forcing
the outputs to the steady state levels as shown in the function table.
Absolute Maximum Ratings:
(Note 1)
Supply Voltage, V
CC
7V.................................................................
Input Voltage 7V.......................................................................
Operating Temperature Range, T
A
0C to +70C............................................
Storage Temperature Range, T
stg
−65C to +150C........................................
Note 1. Voltage values are with respect to network ground terminal.
Recommended Operating Conditions:
Parameter Symbol Min Typ Max Unit
Supply Voltage V
CC
4.75 5.0 5.25 V
High−Level Input Voltage V
IH
2 − − V
Low−Level Input Voltage V
IL
− − 0.8 V
High−Level Output Current I
OH
− − −0.4 mA
Low−Level Output Current I
OL
− − 8 mA
Clock Frequency f
clock
0 − 30 MHz
Pulse Duration
CLK High
t
w
20 − − ns
PRE or CLR Low 25 − − ns
Setup Time Before CLK 
Data High or Low
t
su
20 − − ns
CLR Inactive 20 − − ns
PRE Inactive 25 − − ns
Hold Time Data After CLK  t
h
0 − − ns
Operating Temperature Range T
A
0 − +70 C