Datasheet

Description (Cont’d):

Subtraction is accomplished by 1’s complement addition where the 1’s complement of the substrahend

is generated internally. The resultant output is A−B−1, which requires an end−around or forced carry to

provide A−B.

The NTE74LS181 can also be utilized as a comparator. The A = B output is internally decoded from

the function outputs (F0, F1, F2, F3) so that when two words of equal magnitude are applied at the

A and b inputs, it will assume a high level to indicate equality (A = B). The ALU must be in the subtract

mode with C

= H when performing this comparison. The A = B output is open−collector so that it can

be wire−AND connected to give a comparison fo more than four bits. The carry output (C

n+4

) can also

be used to supply relative magnitude information. Again, the ALU must be placed in the subtract mode

by placing the function select inputs S3, S2, S1, S0 at L, H, H, L, respectively.

Input C

Output C

n+4

Active−Low Data Active−High Data

H H A  B A  B

H L A < B A > B

L H A > B A < B

L L A  B A  B

This circuit has been designed to not only incorporate all of the designer’s requirements for arithmetic

operations, but also to provide 16 possible functions of two Boolean variables without the use of exter-

nal circuitry. These logic functions are selected by use of the four function−select inputs (S0, S1, S2,

S3) with the mode−control input (M) at a high level to disable th internal carry. The 16 logic functions

are detailed in tables 1 and 2 and include exclusive−OR, NAND, AND, NOR, and OR functions.

Signal Designations:

The NTE74LS181 together with the ’182 and ’S182 can be used with the signal designations of either

Figure 1 or Figure 2. The inversion indicators (O) and the bars over the terminal letter symbols (e.g.,

) each indicate that the associated input or output is active with respect to the selected function of

the device when the input output is low. That is, a low C

means “do carry” while a high means “do not

carry”.

The logic functions and arithmetic operations obtained with signal designations of Figure 1 are given

in Table 1; those obtained with signal designations of Figure 2 are given in Table 2.