Datasheet
Switching Characteristics: (V
CC
= 5V, T
A
= +25C, C
L
= 15pF, R
L
= 2k unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Propagation Delay Time
(From C
n
Input to C
n+4
Output)
t
PLH
− 18 27 ns
t
PHL
− 13 20 ns
Propagation Delay Time
(From Any A
or B Input to C
n+4
Output)
t
PLH
M = 0V, S0 = S3 = 4.5V,
S1 = S2 = 0V (SUM
Mode)
− 25 38 ns
t
PHL
− 25 38 ns
Propagation Delay Time
(From Any A
or B Input to C
n+4
Output)
t
PLH
M = 0V, S0 = S3 = 0V,
S1 = S2 = 4.5V (DIFF
Mode)
− 27 41 ns
t
PHL
− 27 41 ns
Propagation Delay Time
(From C
n
Input to Any F Output)
t
PLH
M = 0V,
(SUM
or DIFF Mode)
− 17 26 ns
t
PHL
− 13 20 ns
Propagation Delay Time
(From Any A
or B Input to G Output)
t
PLH
M = 0V, S0 = S3 = 4.5V,
S1 = S2 = 0V (SUM
Mode)
− 19 29 ns
t
PHL
− 15 23 ns
Propagation Delay Time
(From Any A
or B Input to G Output)
t
PLH
M = 0V, S0 = S3 = 0V,
S1 = S2 = 4.5V (DIFF
Mode)
− 21 32 ns
t
PHL
− 21 32 ns
Propagation Delay Time
(From Any A
or B Input to P Output)
t
PLH
M = 0V, S0 = S3 = 4.5V,
S1 = S2 = 0V (SUM
Mode)
− 20 30 ns
t
PHL
− 20 30 ns
Propagation Delay Time
(From Any A
or B Input to P Output)
t
PLH
M = 0V, S0 = S3 = 0V,
S1 = S2 = 4.5V (DIFF
Mode)
− 20 30 ns
t
PHL
− 22 33 ns
Propagation Delay Time
(From Any A
i
or B
i
Input to F
i
Output)
t
PLH
M = 0V, S0 = S3 = 4.5V,
S1 = S2 = 0V (SUM
Mode)
− 21 32 ns
t
PHL
− 13 20 ns
Propagation Delay Time
(From Any A
i
or B
i
Input to F
i
Output)
t
PLH
M = 0V, S0 = S3 = 0V,
S1 = S2 = 4.5V (DIFF
Mode)
− 21 32 ns
t
PHL
− 21 32 ns
Propagation Delay Time
(From Any A
i
or B
i
Input to F
i
Output)
t
PLH
M = 4.5V
(Logic Mode)
− 22 33 ns
t
PHL
− 26 38 ns
Propagation Delay Time
(From Any A
or B Input to A = B Output)
t
PLH
M = 0V, S0 = S3 = 0V,
S1 = S2 = 4.5V (DIFF
Mode)
− 33 50 ns
t
PHL
− 41 62 ns
Typical Addition Times:
Number
of Bits
Additional Times Package Count
Carry Method
Between ALU’s
Using ’LS181
and ’182
Arithmetic/
Logic Units
Look−Ahead
Carry Generators
1 to 4 24ns 1 − None
5 to 8 40ns 2 − Ripple
9 to 16 44ns 3 or 4 1 Full Look−Ahead
17 to 64 68ns 5 to 16 2 to 5 Full Look−Ahead
Description (Cont’d):
The NTE74LS181 will accommodate active−high or active−low data if the pin designations are
interpreted as follows:
Pin Number
2 1 23 22 21 21 19 18 9 10 11 13 7 16 15 17
Active−Low Data (Table 1) A
0
B
0
A
1
B
1
A
2
B
2
A
3
B
3
F
0
F
1
F
2
F
3
C
n
C
n+4
P G
Active−High Data (Table 2) A
0
B
0
A
1
B
1
A
2
B
2
A
3
B
3
F
0
F
1
F
2
F
3
C
n
C
n+4
X Y