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NTE741LS181

Integrated Circuit

TTL − Arithmetic Logic Unit/Function Generator

Description:

The NTE74LS181 is an arithmetic logic unit (ALU)/function generator in a 24−Lead DIP type package

that has the complexity of 75 equivalent gates on a monolithic chip. This circuit performs 16 binary

arithmetic operations on two 4−bit words as shown in Tables 1 and 2. These operations are selected

by the four function−select lines (S0, S1, S2, S3) and include addition, subtraction, decrement, and,

and straight transfer. When performing arithmetic manipulations, the internal carries must be enabled

by applying a low−level voltage to the mode control input ((M). A full carry look−ahead scheme is

made available in this device for fast, simultaneous carry generation by means of two cascade−out-

puts (Pin15 and Pin17) for the four bits in the package. When used in conjunction with the NTE74182

or NTE74S182, full carry look−ahead circuits, high−speed arithmetic operations can be performed.

The typical addition times shown in the Typical Additional Times table illustrate the little additional time

required for addition of longer words when full carry look−ahead is employed.

If high speed is not of importance, a ripple−carry input (C

) and a ripple−carry output (C

n+4

) are available.

However, the ripple−carry delay has also been minimized so that arithmetic manipulations for small word

lengths can be performed without external circuitry.

Features:

D Full Look−Ahead for High Speed Operations on Long Words

D Input Clamping Diodes Minimize Transmission−Line Effects

D Darlington Outputs Reduce Turn−Off Time

D Arithmetic Operating Modes:

Addition

Subtraction

Shift Operand A One Position

Magnitude Comparison

Plus Twelve Other Arithmetic Operations

D Logic Function Modes:

Exclusive−OR

Comparator

AND, NAND, OR, NOR

Plus Ten Other Logic Operations

Absolute Maximum Ratings:

= 0 to +70C unless otherwise specified)

Supply Voltage (Note 1), V

7V.........................................................

Input Voltage, V

5.5V..................................................................

Interemitter Voltage (Note 2) 5.5V........................................................

Operating Ambient Temperature Range, T

0 to +70C.....................................

Storage Temperature Range, T

stg

−65 to +150C..........................................

Note 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.

Note 2. This is the voltage between two emitters of a multiple−emitter transistor. For this circuit, this

rating applies to each A

input in conjunction with inputs S2 or S3, and to each B input in con-

junction with inputs S0 or S3.

Summary of content (8 pages)

PAGE 1
NTE741LS181 Integrated Circuit TTL − Arithmetic Logic Unit/Function Generator Description: The NTE74LS181 is an arithmetic logic unit (ALU)/function generator in a 24−Lead DIP type package that has the complexity of 75 equivalent gates on a monolithic chip. This circuit performs 16 binary arithmetic operations on two 4−bit words as shown in Tables 1 and 2.
PAGE 2
Recommended Operation Conditions: Parameter Symbol Min Typ Max Unit Supply Voltage VCC 4.75 5.0 5.25 V High−Level Output Current (All outputs except A = B) IOH − − −400 A Low−Level Output Current IOL − − 8 mA Operating Ambient Temperature TA 0 − 70 C Electrical Characteristics: (TA = 0 to +70C, Note 3, Note 4 unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit High−Level Input Voltage VIH 2 − − V Low−Level Input Voltage VIL − − 0.
PAGE 3
Switching Characteristics: (VCC = 5V, TA = +25C, CL = 15pF, RL = 2k unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Propagation Delay Time (From Cn Input to Cn+4 Output) tPLH − 18 27 ns tPHL − 13 20 ns Propagation Delay Time (From Any A or B Input to Cn+4 Output) tPLH M = 0V, S0 = S3 = 4.5V, S1 = S2 = 0V (SUM Mode) − 25 38 ns − 25 38 ns Propagation Delay Time (From Any A or B Input to Cn+4 Output) tPLH M = 0V, S0 = S3 = 0V, S1 = S2 = 4.
PAGE 4
Description (Cont’d): Subtraction is accomplished by 1’s complement addition where the 1’s complement of the substrahend is generated internally. The resultant output is A−B−1, which requires an end−around or forced carry to provide A−B. The NTE74LS181 can also be utilized as a comparator. The A = B output is internally decoded from the function outputs (F0, F1, F2, F3) so that when two words of equal magnitude are applied at the A and b inputs, it will assume a high level to indicate equality (A = B).
PAGE 5
Figure 1: S3 S2 A0 S1 S0 F0 A1 F1 A2 F2 A3 F3 B0 ’LS181 B1 A=B B2 Cn+4 B3 G Cn P M Cn+x Cn Cn+y G0 Cn+z G1 ’182 or ’S182 G2 G3 G P0 P1 P P2 P3 Table 1: Active−Low Data Selection M=H Logic Functions M = L; Arithmetic Operations S3 S2 S1 S0 Cn = L (no carry) Cn = H (with carry) L L L L F=A F = A MINUS 1 F=A L L L H F = AB F = AB MINUS 1 F = AB L L H L F=A+B F = AB MINUS 1 F = AB L L H H F=1 F = MINUS 1 (2’s COMPL) F = ZERO L H L L F=A+B
PAGE 6
Figure 2: S3 S2 A0 S1 S0 F0 A1 F1 A2 F2 A3 F3 B0 ’LS181 B1 A=B B2 Cn+4 B3 Y Cn X M Cn+x Cn Cn+y Y0 Cn+z Y1 ’182 or ’S182 Y2 Y3 X0 Y X1 X2 X X3 Table 2: Active−High Data Selection M=H Logic Functions M = L; Arithmetic Operations S3 S2 S1 S0 Cn = H (no carry) Cn = L (with carry) L L L L F=A F=A F = A PLUS 1 L L L H F=A+B F=A+B F = (A + B) PLUS 1 L L H L F = AB F=A+B F = (A + B) PLUS 1 L L H H F=0 F = MINUS 1 (2’s COMPL) F = ZERO L H L L F
PAGE 7
Parameter Measurement Information: SUM Mode Test Table Function Inputs: S0 = S3 = 4.5V, S1 = S2 = M = 0V Parameter tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Input Under Test Ai Other Input Same Bit Apply 4.5V Apply GND Bi None Other Data Inputs Apply 4.
PAGE 8
Parameter Measurement Information (Cont’d): Logic Mode Test Table Function Inputs: S1 = S2 = M = 4.5V, S0 = S3 = 0V Parameter Input Under Test tPLH tPHL tPLH tPHL Ai Bi Other Input Same Bit Apply 4.5V Apply GND Bi None Ai None Other Data Inputs Apply 4.