Datasheet

NTE7495
Integrated Circuit
TTL − 4−Bit Parallel−Access Shift Register
Description:
The NTE7495 is 4−bit register in a 14−Lead DIP type package that features parallel and serial inputs,
parallel outputs, mode control, and two clock inputs. This device hs three output modes of operation:
Parallel (broadside) Load
Shift Right (the direction Q
A
toward Q
D
)
Shift Left (the direction Q
D
toward Q
A
)
Parallel loading is accomplished by applying the four bits of data and taking the mode control input
high. The data is loaded into the associated flip−flops and appears at the outputs after the high−to−low
transition of the clock−2 input. During loading, the entry of serial data is inhibited.
Shift right is accomplished on the high−to−low transition of clock 1 when the mode control is low;
shift left is accomplished on the high−to−low transition of clock 2 when the mode control is high by
connecting the output of each flip−flop to the parallel input of the previous flip−flop (Q
D
to input C,
etc.) and serial data is entered at input D. The clock input may be applied commonly to clock 1 and
clock 2 if both modes can be clocked from the same source. Changes at the mode control input
should normally be made while both clock inputs are low; however, conditions described in the last
three lines of the function table will also ensure that register contents are protected.
Absolute Maximum Ratings:
(Note 1)
Supply Voltage, V
CC
7V.................................................................
Input Voltage, V
IN
5.5V.................................................................
Interemitter Voltage (Note 2) 5.5V........................................................
Power Dissipation 195mW..............................................................
Operating Temperature Range, T
A
0C to +70C............................................
Storage Temperature Range, T
stg
−65C to +150C........................................
Note 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
Note 2. This is the voltage between two emitters of a multiple−emitter input transistor. This rating
applies between the clock−2 and th mode control input.