Owner's manual

Functional description 811
• microprocessor
• CPU interface
• external timing interface
The main functional blocks of the NTAK20 architecture include:
• phase difference detector circuit
•
digital phase-lock loop
• clock detection circuit
• digital-to-analog converter
• CPU MUX bus interface
•
signal conditioning drivers and buffers
• sanity timer
•
microprocessor
•
CPU interface
•
external timing interface
A description of each block follows.
The main functional blocks of the NTAK20 architecture include:
• phase difference detector circuit
•
digital Phase Locked Loop (PLL)
• clock detection circuit
•
digital-to-analog converter
•
CPU MUX bus interface
•
signal conditioning drivers and buffers
• sanity timer
• microprocessor
• CPU interface
• external timing interface
Phase difference detector circuit
This circuit, under firmware control, enables a phase difference
measurement to be taken between the reference entering the PLL and
the system clock.
Nortel Communication Server 1000
Circuit Card Reference
NN43001-311 02.06 Standard
27 August 2008
Copyright © 2003-2008 Nortel Networks
.