Datasheet

Revision 1.5 Page 23 of 41
nRF905 Product Specification
9.4 RF – Configuration Register Description
Parameter Bitwidth Description
CH_NO 9 Sets center frequency together with HFREQ_PLL (default =
001101100
b
= 108
d
).
f
RF
= ( 422.4 + CH_NO
d
/10)*(1+HFREQ_PLL
d
) MHz
HFREQ_
PLL
1 Sets PLL in 433 or 868/915MHz mode (default = 0).
'0' – Chip operating in 433MHz band
'1' – Chip operating in 868 or 915 MHz band
PA_PWR 2 Output power (default = 00).
'00' -10dBm
'01' -2dBm
'10' +6dBm
'11' +10dBm
RX_RED_
PWR
1 Reduces current in RX mode by 1.6mA. Sensitivity is reduced
(default = 0).
'0' – Normal operation
'1' – Reduced power
AUTO_
RETRAN
1 Retransmit contents in TX register if TRX_CE and TXEN are
high (default = 0).
'0' – No retransmission
'1' – Retransmission of data packet
RX_AFW 3 RX-address width (default = 100).
'001' – 1 byte RX address field width
'100' – 4 byte RX address field width
TX_AFW 3 TX-address width (default = 100).
'001' – 1 byte TX address field width
'100' – 4 byte TX address field width
RX_PW 6 RX-payload width (default = 100000).
'000001' – 1 byte RX payload field width
'000010' – 2 byte RX payload field width
.
'100000' – 32 byte RX payload field width
TX_PW 6 TX-payload width (default = 100000).
'000001' – 1 byte TX payload field width
'000010' – 2 byte TX payload field width
.
'100000' – 32 byte TX payload field width
RX_
ADDRESS
32 RX address identity. Used bytes depend on RX_AFW (default =
E7E7E7E7
h
).
UP_CLK_
FREQ
2 Output clock frequency (default = 11).
'00' – 4MHz
'01' – 2MHz
'10' – 1MHz
'11' – 500kHz
UP_CLK_
EN
1 Output clock enable (default = 1).
'0' – No external clock signal available
'1' – External clock signal enabled