Datasheet

Page 48 of 161
nRF8001 Product Specification
Revision 1.2
14.4 Reset
The RESET line should be held low for a minimum duration of 200 ns for the nRF8001 to reset.
14.5 Antenna Matching and Balun
The ANT1 and ANT2 pins provide a balanced RF connection to the antenna. The pins must have a DC path
to
VDD_PA, either through an RF choke or through the center point in a balanced dipole antenna. A load
impedance at
ANT1 and ANT2 of 15  + j88  is recommended for maximum output. A load impedance of
50  can be obtained by fitting a simple matching network between the load and the
ANT1 and ANT2 pins.
A recommended matching network for 50  load impedance is described in chapter 17 on page 51
.
14.6 DC/DC Converter requirements
The DC/DC converter requires three external components, two inductors and one decoupling capacitor,
see Figure 21. on page 51
. The inductors should have a low serial resistance (< 1.0 ) and must have a
maximum DC current rating of at least 50 mA. The capacitors should have low serial resistance.
14.7 PCB layout and decoupling guidelines
A well designed PCB is necessary to achieve good RF performance. A poor layout can lead to loss of
performance or functionality. A fully qualified RF-layout for nRF8001 and its surrounding components,
including matching networks, can be downloaded from www.nordicsemi.com.
A PCB with a minimum of two layers including a ground plane is recommended for optimum performance.
The nRF8002 DC supply voltage should be decoupled as close as possible to the VDD pins with high
performance RF capacitors. See the schematics layout in chapter 17 on page 51 for recommended
decoupling capacitor values. The nRF8001 supply voltage should be filtered and routed separately from
the supply voltages of any digital circuitry.
Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD
bypass capacitors must be connected as close as possible to the nRF8001 IC. For a PCB with a topside
RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom
ground plane, the best technique is to have via holes as close as possible to the VSS pads. A minimum of
one via hole should be used for each VSS pin.
Full swing digital data or control signals should not be routed close to the crystal or the power supply lines.