Datasheet

PRELIMINARY PRODUCT SPECIFICATION
nRF24L01 Single Chip 2.4 GHz Radio Transceiver
Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone [phone] - Fax [phone]
Revision: 1.2 Page 23 of 39 March 2006
Address
(Hex)
Mnemonic Bit Reset
Value
Type Description
‘0001’ – Wait 500+86uS
‘0010’ – Wait 750+86uS
……..
‘1111’ – Wait 4000+86uS
(Delay defined from end of transmission
to start of next transmission)
14
ARC 3:0 0011 R/W Auto Retransmit Count
‘0000’ –Re-Transmit disabled
‘0001’ – Up to 1 Re-Transmit
on fail of AA
……
‘1111’ – Up to 15 Re-Transmit
on fail of AA
05 RF_CH RF Channel
Reserved 7 0 R/W Only '0' allowed
RF_CH 6:0 0000010 R/W Sets the frequency channel nRF24L01
operates on
06 RF_SETUP RF Setup Register
Reserved 7:5 000 R/W Only '000' allowed
PLL_LOCK 4 0 R/W Force PLL lock signal. Only used in test
RF_DR 3 1 R/W Data Rate
‘0’ – 1 Mbps
‘1’ – 2 Mbps
RF_PWR 2:1 11 R/W Set RF output power in TX mode
'00' – -18 dBm
'01' – -12 dBm
'10' – -6 dBm
'11' – 0 dBm
LNA_HCURR 0 1 R/W Setup LNA gain
07 STATUS Status Register (In parallel to the SPI
instruction word applied on the MOSI
pin, the STATUS register is shifted
serially out on the MISO pin)
Reserved 7 0 R/W Only '0' allowed
RX_DR 6 0 R/W Data Ready RX FIFO interrupt. Set high
when new data arrives RX FIFO
15
.
Write 1 to clear bit.
TX_DS 5 0 R/W Data Sent TX FIFO interrupt. Set high
when packet sent on TX. If AUTO_ACK
is activated, this bit will be set high only
when ACK is received.
Write 1 to clear bit.
MAX_RT 4 0 R/W Maximum number of TX retries interrupt
Write 1 to clear bit. If MAX_RT is
set it must be cleared to enable
further communication.
RX_P_NO 3:1 111 R Data pipe number for the payload
14
Accurate formula for delay from start of transmission, to start of re-transmission:
TRD (us) = 250us * (ARD+1) + 4us *(AW + PW + CRCW) +138,5us.
TRD= total retransmit delay, AW=Address Width (#bytes), PW=Payload Width(#bytes)
, CRCW= CRC Width (#bytes)
15
The Data Ready interrupt is set by a new packet arrival event. The procedure for handling this
interrupt should be: 1) read payload via SPI, 2) clear RX_DR interrupt, 3) read FIFO_STATUS to
check if there are more payloads available in RX FIFO, 4) if there are more data in RX FIFO, repeat
from 1).