Datasheet

PRELIMINARY PRODUCT SPECIFICATION
nRF24L01 Single Chip 2.4 GHz Radio Transceiver
Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone [phone] - Fax [phone]
Revision: 1.2 Page 19 of 39 March 2006
DEVICE CONFIGURATION
All configuration of nRF24L01 is defined by values in some configuration registers.
All these registers are writable via the SPI interface.
SPI Interface
The SPI interface is a standard SPI interface with a maximum data rate of 10Mbps.
Most registers are readable.
SPI Instruction Set
The available commands to be used on the SPI interface are shown below. Whenever
CSN is set low the interface expects an instruction. Every new instruction must be
started by a high to low transition on CSN.
In parallel to the SPI instruction word applied on the MOSI pin, the STATUS register
is shifted serially out on the MISO pin.
The serial shifting SPI commands is on the format:
<Instruction word: MSBit to LSBit (one byte)>
<Data bytes: LSByte to MSByte, MSBit in each byte first>
See Figure 8 and Figure 9.
Instruction Name Instruction
Format
[binary]
# Data
Bytes
Operation
R_REGISTER
000A AAAA
1 to 5
LSByte first
Read registers. AAAAA = 5 bit Memory Map Address
W_REGISTER
001A AAAA
1 to 5
LSByte first
Write registers. AAAAA = 5 bit Memory Map Address
Executable in power down or standby modes only.
R_RX_PAYLOAD
0110 0001
1 to 32
LSByte first
Read RX-payload: 1 – 32 bytes. A read operation will
always start at byte 0. Payload will be deleted from FIFO
after it is read. Used in RX mode.
W_TX_PAYLOAD
1010 0000
1 to 32
LSByte first
Used in TX mode.
Write TX-payload: 1 – 32 bytes. A write operation will
always start at byte 0.
FLUSH_TX
1110 0001
0 Flush TX FIFO, used in TX mode
FLUSH_RX
1110 0010
0 Flush RX FIFO, used in RX mode
Should not be executed during transmission of
acknowledge, i.e. acknowledge package will not be
completed.
REUSE_TX_PL
1110 0011
0 Used for a PTX device
Reuse last sent payload. Packets will be repeatedly resent
as long as CE is high.
TX payload reuse is active until W_TX_PAYLOAD or
FLUSH TX is executed. TX payload reuse must not be
activated or deactivated during package transmission
NOP
1111 1111
0 No Operation. Might be used to read the STATUS register
Table 8 Instruction set for the nRF24L01 SPI interface.
The W_REGISTER and R_REGISTER may operate on single or multi-byte registers.
When accessing multi-byte registers one will read or write MSBit of LSByte first. The