User Guide

• RDS/RBDS encoder

• Loop and monopole antenna support with self-calibrated capacitor tuning.

• Programmable transmit level.

• Audio dynamic range control.

System block diagram

Figure 42 FMTx 2.0 system block diagram

The figure shows a basic system block diagram for the FMTx 2.0 implementation. _SEN is shown here

unconnected since this pin decides which I2C address is used depending on if this pin is pulled low or high.

On RM-348 the _SEN is pulled high by connecting it to VIO.

RM-348 uses a loop antenna which is buried in the B-cover of the device. The loop antenna also acts as the

tuning inductor which is required by the Si4713 chip. The location of the antenna in the B-cover means that

no ESD protection is required to prevent damage to the Si4713 device.

RM-348; RM-349; RM-350

FMTx 2.0 Technical Description

Page 6 –6 COMPANY CONFIDENTIAL Issue 2