User Guide

32k Sleep Clock is always powered on after startup. Sleep clock is used by RAP and the application processor

for low-power operation.

SMPS Clk is 2.4 MHz clock line from RAP to EM ASIC N2300 used for switch mode regulator synchronizing in

active mode. In deep sleep mode, when VCTCXO is off, this signal is set to '0'-state.

BT Clk is 38.4 MHz signal from the RF ASIC to the Bluetooth system.

Figure 37 Clocking scheme

Figure 38 Clocking scheme

Bluetooth/FM module

The device has a module version of Bluetooth, in which BT and FM radio solutions are combined to a single

BTHFM module. The module includes all external components except the antenna. However, the two solutions

are electrically isolated from one another.

RA-6

System Module

Page 6 –10 COMPANY CONFIDENTIAL Issue 1