User Guide

Figure 85 WLAN and BT block diagram

WLAN signals and interfaces

WLAN interface signals are listed in following table. These signals can be grouped to following categories:

host interface 6 lines, clocking interface 3 lines, WLAN/BT coexistence interface 4 lines and power 2 lines.

The serial interface is connected to APE McBSP interface block.

WLAN/BT coexistence signaling interface (CXS) enables time shared operation of BT and WLAN transceivers

so that the user perceives simultaneous operation of both systems.

Signal names in the table refer to RM-10/24 shematics pin names.

WLAN BB/MAC

The baseband chip implements OFDM/CCK digital baseband processor and ARM9-based MAC with internal

SRAM memories.

Regulators

Switching stepdown regulator generates the MAC/BB digital core supply at 1.2 V.

Two separate LDOs at 1.8 V output supply the VCO and the transceiver. The main 1.8 V supply is used for

transceiver analog parts, ADC/DAC and digital circuits inside the transceiver.

IrDA

IrDA specifies a low-cost, reliable, fully digital peer-to-peer data link between IrDA units at data rates from

9600 bits/s to 115 kbit/s. The link is based on the serial transmission of data as pulses of infra red light at

the wave length of 870nm and angles of +-15degrees at the range 0 - 50 to 100 cm. Because these restrictions

and the optical nature of the link, the transmission is not omnidirectional but focused and only reaches a

peer at a limited line-of-sight distance from the transmitter thus not disturbing any other units in the

neighbourhood.

RM-10;RM-24

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