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• WLAN

• LDO

• discrete regulators

• backlight SMPS

All the above are powered by the main battery voltage.

Battery voltage is also used on the RF side for power amplifiers (GSM PA & WCDMA PA) and for Rx/Tx ASICs.

Discrete power supplies are used to generate 2.8V to BT/WLAN oscillator, 1.5V for the LCD controller voltage,

1.05V/1.4V for application processor and 18V for the backlight LEDs.

The device supports both 1.8V/3V SIM cards which are powered by EM ASIC N2200 / VSIM1. EM ASIC N2200s

VSIM2 is used to power RS MMC 1.8V only. USB accessories which needs power from the device are powered

by EM ASIC N2300 / VOUT.

External SMPS is used to drive LEDs, SMPS is controlled by EM ASIC N2300 and powered by battery voltage.

System power-up

After inserting the main battery, regulators started by HW are enabled. SW checks, if there is some reason to

keep the power on. If not, the system is set to power off state by watchdog. Power up can be caused by the

following reasons:

• Power key is pressed

• Charger is connected

• RTC alarm occurs

• MBUS wake-up

Clocking scheme

Two main clocks are provided to the system: 38.4MHz RF clock produced by VCTCXO in RF section and

32.768kHz sleep clock produced by EM ASIC (N2200) with an external crystal.

RF clock is generated only when VCTCXO is powered on by EM ASIC (N2200) regulator. Regulator itself is

activated by SleepX signals from both RAP and application processor. When both CPUs are on sleep, RF clock

is stopped.

RF clock is used by RAP that then provides (divided) 19.2MHz SysClk further to OMAP. Both RAPG and application

processor have internal PLLs which then create clock signals for other peripheral devices/interfaces like RS

MMC, SIM, CCP, I2C and memories.

32k Sleep Clock is always powered on after startup. Sleep clock is used by RAP and OMAP for low-power

operation.

SMPS Clk is 2.4MHz clock line from RAP to EM ASIC (N2300) used for switch mode regulator synchronizing in

active mode. In deep sleep mode, when VCTCXO is off, this signal is set to '0'-state.

BT Clk is a 38.4MHz clock. BT ASIC BRF6150 requires a system clock which it uses to derive all its internal

timing. The external TCXO clock oscillator is used for the system clock with a sinusoidal output.

CLK600 is 600KHz signal from EM ASIC (N2300) to APE VCORE SMPS. The clock source is internal RC oscillator

in EM ASIC (N2300) (during the power-up sequence and sleep) or RAP SMPS Clk divided by 4 after the power-

up sequence.

RM-49

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