User Guide

PAMS
Technical Documentation
RAE-3
8. Troubleshooting
Page 8 – 85
Issue 1 06/01
Figure 73. GENSCLK signal.
GENSCLK signal (Figure 73 ). It should look like this when LCDEN signal is ac-
tive. There is also a 2.16MHz clock signal, but it is targeted for CCONT.
Table 5. Signals and pins
Signal Pin no.
LCDEN 12
GENSDIO 9
GENSCLK 11
LCDRSTX 14
Table above: Signals and corresponding pins.