User Guide

PAMS
Technical Documentation
RAE-3
3. RF+System Module BL8
Page 3 – 31
issue 1 06/01
System to interface
In following chapters the blocks of system HW in SYSTEM part of BL8 sche-
matics and functions related to each interface are described.
The blocks include: CPU, MEMORIES, MMC, IRDA, UI, SYSCON, AUDIO_RFI
and POWER.
Component placement diagrams are in the A3 section.
CPU block
Main components in the CPU block comprise:
– MADLinda ASIC (D300), package 240 m*BGA
– Hall switch TLE4916 (V301)
MADLinda is the main ASIC for RAE-3’s single processor system. MADLinda is
used as engine processor for both CMT and PDA functions. The pins are ot
listed because it is not possible to access them except at measurement points.
Hall sensor switch is used to detect lid position (open/close). Magnet for detec-
tion is in lid part of RAE-3. Hall device’s open drain output is pulled up with ex-
ternal 100k
W resistor (R302). Output goes to low state when the sensor is not in
magnetic field (lid open).
MEMORIES block
Main components in the block include:
– three 2Mx16 (32Mbit) Flash memories (D351, D352, D353)
– SDRAM 4Mx16 (64Mbit) (D350)
– Serial Flash 32Mbit (D354)
XIP Memories
The MPU program code resides in three Flash memories. 128kBytes PPM area
for language depend program parts is locate to one of the XIP flashes. Also
4*8kBytes PMM area and 4*8kBytes for EEPROM emulation (EEEMU) is lo-
cated to that same flash device.
Flashes are 4Mbyte (2Mx16) 80ns asynchronous ’Advanced Boot Block’ de-
vices packed in 48 pin CSP (VFBGA48).
XIP memories are supplied from 2.8V VBB and I/O voltage from 1.8V Vcore.