User Guide

NSD-5
3. System Module PAMS Technical Documentation
Page 50 Nokia Corporation Issue 1 05/02
Table 16: Control bits vs data location
Table 17: 15-bit programmable reference divider ratio (R Counter)
R1 to R15: These bits select the divide ratio of the programmable reference divider. Data
is shifted in MSB first.
Programmable Divider (N Counter)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit program-
mable counter (B counter). If the control bits are 10 or 11 (10 for RF counter), data is
transferred from the 22-bit shift register into a 4-bit or 7-bit latch (which sets the swal-
low [A] counter) and an 11-bit latch (which sets the 11-bit programmable [B] counter),
MSB first. Serial data format follows. The IF N counter bits 5, 6, and 7 are “don’t care”
bits. The RF N counter does not have any “don’t care” bits.
Control Bits DATA Location
C1 C2
0 0 IF R Counter
0 1 RF R Counter
1 0 IF N Counter
1 1 RF N Counter
Divide
Ratio
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3 0 0 0 0 0 0 000000011
4 0 0 0 0 0 0 000000100
. . . . . . . .........
237671 1 1 1 1 1 111111111