User Guide

NSD-5
3. System Module PAMS Technical Documentation
Page 24 Nokia Corporation Issue 1 05/02
CAFE/MAD4 Serial Data Interface
MAD/CAFE serial data interface allows both DSP and MCU processors within MAD4 to
read/write CAFE control registers. It also provides a serial interface with MAD4 for the
CODEC to receive and transmit audio data.
The serial data is transferred at a 320KHz data rate. The frame structure for the serial
interface is based on an 8 kHz wide period where the control data is transferred in the
first half of the frame period and the audio data is transferred in the second half of the
frame period for both directions.
For details on the interface protocol, refer to the CAFE ASIC specification.
CAFE/MAD4 TX Interface
The MAD/CAFE TX interface consists of an 8-bit data bus output from MAD4 to CAFE to
be D/A converted to analog signal. The data transfer rate is 9.8304 MHz. The data to be
transmitted is clocked out of MAD4 at the rising edge of the 9.8304 MHz clock and
clocked into CAFE at the falling edge of the clock.
In CDMA mode, the data consists of alternating TXI and TXQ data. IQSel signal is used by
CAFE to select the appropriate I/Q component. When IQSel = ‘1’, the data is TXI compo-
nent; when IQSel = ‘0’, the data is TXQ component.
For more information, see CAFE design specification.
TX Gate Enable
CAFE_TX_GATE is an active high-enable signal used to enable/disable CAFE internal TX
DACs. This signal is provided by the CDMA transmit block within MAD4 and is synchro-
nized to the 9.8304MHz clock.
CAFE/MAD4 Clock/Reset Interface
The active low signal (RESETX) is used as an asynchronous reset for CAFE to set all inter-
nal registers to a known state when the system starts up.
CAFE provides MAD4 with two clocks. One is the system clock, which is 19.2MHz. The
other is a CDMA clock that is 9.8304MHz. MAD4 generates its internal lower rate clocks
for interface data transmission and reception. It also supplies an 8 kHz frame sync pulse
(CAFESIO2) to CAFE, which is used to create its own internal clocks for interface trans-
mission and reception. These are synchronized to the equivalent clocks within the MAD
ASIC.
The following figure (Figure 12) shows the correlation and alignment of internal/external
clocks within these two ASICs.