User Guide

PAMS Technical Documentation 3. System Module
NSD-5
Issue 1 05/02 Nokia Corporation Page 23
Tf:Falling time
Tr:Rising time
T
SDOD:
Delay time for data from CAFE to MAD4, from CLK19M20 to data valid
T
SDIH:
Hold time for serial data from MAD4 to CAFE
T
SDISU:
Setup time for serial data from MAD4 to CAFE
T
IQSU:
Setup time for IQSEL
T
TXGON:
TXGATE turn on time before first valid data
T
TXGOFF:
TXGATE turn off time after last valid data
T
TXGS:
Setup time for TXGATE
T
TXGH:
Hold time for TXGATE
T
DH:
Hold time for TXD(7:0)
T
DSU:
Setup time for TXD(7:0)
T
DRXD:
Delay from CLK9M80 falling edge to valid RX data
T
per:
Clock period
Table 3: MAD/CAFE interface signals
CAFESIO(2)
“1” (V)
“0” (V)
Tf (ns)
Tr (ns)
2.24
0
TBD
TBD
2.70
0.30
Vbb
0.62
TBD
TBD
8 kHz frame sync clock from
MAD to CAFE to synchronize
CAFE serial interface to MAD
IQSEL
“1” (V)
“0” (V)
T
IQSU
(ns)
2.24
0
20
2.70
0.30
Vbb
0.62
I and Q selection from MAD to
CAFE. “1” is for I data and “O” is
from Q and AMPS data
CAFE_TX_GATE
“1” (V)
“0” (V)
T
TXGON
T
TXGOFF
T
TXGS
(ns)
T
TXGH
(ns)
2.24
0
10 us
10 us
10
10
2.70
0.30
Vbb
0.62
CAFE internal transmit enable
signal from MAD to CAFE (Active
“High”)
TXD(7:0)
“1” (V)
“0” (V)
T
DH
(ns)
T
DSU
(ns)
2.24
0
20
20
2.70
0.30
Vbb
0.62 8-bit parallel transmit data from
MAD to CAFE for both CDMA and
AMPS modes
RXD(11:0)
“1” (V)
“0” (V)
T
DRXD
(ns)
2.24
0
2.70
0.30
Vbb
0.62
20
12-bit parallel receives data
from CAFE to MAD for both
CDMA and AMPS mode
CLK19M20
“1” (V)
“0” (V)
Tper (ns)
2.24
0
52.08
2.70
0.30
Vbb
0.62
52.08
19.2MHz system clock from CAFE
to MAD
CLK9M83
“1” (V)
“0” (V)
Tper (ns)
2.24
0
101.73
2.70
0.30
Vbb
0.62
101.73
9.8304MHz CDMA system clock
from CAFE to MAD
RESETX
“1” (V)
“0” (V)
Tf (ns)
Tr (ns)
2.24
0
TBD
TBD
2.70
0.30
Vbb
0.62
TBD
TBD
CAFE reset (active “low”) from
MAD to CAFE
Signal Parameter Min Typical Max Function