User Guide

NSD-5
3. System Module PAMS Technical Documentation
Page 16 Nokia Corporation Issue 1 05/02
SYN_CLK
19.2000 MHz clock sent from MAD pin E16 (mdRFSClk) to synthesizer. The rising edge of
the clock is used to clock data into the synthesizer.
SYN_LE1
Loading enable signal from MAD pin F16 (mdRFSLE1) to RF for the dual synthesizer. See
data sheet of the synthesizer for details.
AFC
Signal from MAD pin B17 (mdAFC) to RF VCTCXO to provide 19.2 MHz reference fre-
quency adjustment. It is active in CDMA. When the level is above 1.2V, the frequency is
increased.
High Low Reset/Inactive Current Filtering
Vdd - 0.6V 0 - 0.5V Low/low > 50 ns 1 mA max None
High Low Reset/Inactive Current Filtering
Vdd - 0.6V 0 - 0.5V Low/low > 50 ns 1 mA max None
Type Range Resolution Current Filtering
PDM 0 - 2.8V 9bits @ 9.6MHz clock < 1 mA
BB: RC = 4.7 x 10
-5
Sec
RF: RC = 1.0 x 10
-4
Sec