User Guide

PAMS Technical Documentation 3. System Module
NSD-5
Issue 1 05/02 Nokia Corporation Page 15
MAD4/RF Interface
MAD4/RF Synthesizer Interface
Figure 7: RF/MAD synthesizer interface
Functional Description
Figure 7 defines the MAD4/RF synthesizer interface. The synthesizer interface is capable
of programming National LMX2330L Dual PLL Frequency Synthesizer. See Figure 8 and
Reference 1 for synthesizer timing information such as set-up and hold time.
Figure 8: Synthesizer serial timing
Signal Definitions
SYN_DAT
Data sent from MAD pin E17 (mdRFSData) to the synthesizer divider and counters. It has
2.8V CMOS logic level.
High Low Reset/Inactive Current Filtering
Vdd - 0.6V 0 - 0.5V Low/low > 50 ns 1 mA max None