User Guide

PAMS Technical Documentation 3. System Module
NSD-5
Issue 1 05/02 Nokia Corporation Page 11
Baseband-related External Interface
For detailed information on interfaces to CCONT, CAFE, UI, and accessories, consult the
CCONT, CAFE, and accessory modules in this chapter.
FBUS
FBUS (Fast Bus) is a serial interface between the DSP and data accessories and between
the DSP and multipath analyzer. FBUS also is used as a data path during flash code
downloading. This interface is a full-duplex, asynchronous, two-line bus. Figure 3 illus-
trates the timing for the FBUS.
Figure 3: USART synchronous mode receive (flashing mode)
MBUS
MBUS is a serial data bus of MCU, which is used for flash downloading (clock), testing,
and communication with external devices. Supported baud rates are 9.6, 19.2, 38.4, and
57.6 kbit/s.
JTAG Interface
JTAG Interface is used for MAD4 ASIC emulation including DSP and MCU emulation.
MAD4/External Memories Interface
Functional Description
The external memory consists of FLASH, SRAM, and EEPROM.
FLASH is used to contain the main program code for the MCU and EEPROM default val-
ues (local factory values). It has 2M x 16-bit size and uBGA package.
EEPROM stores tuning parameters and other systems permanently. Its size is 128k bytes.
The external memory interface is shared between the DSP and MCU processors. Both
8-bit and 16-bit external memories are supported. The interface supplies 22 address bits
to allow the MCU/DSP to address up to 4 Mbytes of linear address space for ROM1,
ROM2, and parallel EEPROM and 1 Mbyte of linear address space for SRAM (defined by
the chip-select signals). The DSP will use only the lower 16 bits of the address, and a
bank register is provided to set the 64K-word window for external memory accesses. A
read strobe, write strobe, and four-chip selects are provided for external memories.
Parameter Definition Minimum Maximum Unit
Tsds Data setup to rising edge 90 110 ns
Tsdh Data hold from rising edge 90 110 ns