Programmes After Market Services NSD-5 Series Transceivers 3.
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PAMS Technical Documentation NSD-5 3. System Module Contents Page No Transceiver NSD-5 ........................................................................................................ 7 Introduction ..................................................................................................................7 Modes of Operation .....................................................................................................7 Interconnection Diagram.........................................
NSD-5 3. System Module PAMS Technical Documentation Power Up When Charger Connected ...................................................................... 32 Power Up by IBI ..................................................................................................... 33 Power Up With RTC ............................................................................................... 33 Charging – CHAPS .................................................................................................
PAMS Technical Documentation NSD-5 3. System Module Functional Description of LMX2330L ................................................................... 49 RF-Baseband Connections .........................................................................................55 RF Regulators ............................................................................................................57 Reference .....................................................................................................
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PAMS Technical Documentation NSD-5 3. System Module Transceiver NSD-5 Introduction The NSD-5 is a single-band radio transceiver unit for the CDMA 1900 MHz network. TX operates at 5V. The transceiver consists of System/RF module, User Interface module, and assembly parts. The RF interface, which is documented in this chapter, provides internal signal definition and an internal interface that defines the characteristics of RF intra-module signals.
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PAMS Technical Documentation NSD-5 3. System Module System Module Circuit Description The transceiver electronics consist of the Radio Module, RF + System blocks, the UI PCB, the display module, and audio components. The keypad and the display module are connected to the Radio Module with connectors. System blocks and RF blocks are interconnected with PCB wiring. The Transceiver is connected to accessories via a bottom system connector with charging and accessory control.
NSD-5 3. System Module PAMS Technical Documentation Baseband Module and Interface Block Diagram TX/RX SIGNALS RF SUPPLIES PA SUPPLY SYSTEM CLOCK 19.2MHzCLK Cafe SUPPLY CCONT Cafe SLEEP CLOCK BB SUPPLY 32kHz CLK UI MAD + MEMORIES VBAT CHARGING SWITCH BATTERY AUDIOLINES BASEBAND SYSCON Figure 2: Baseband Module and Interface Block Diagram Baseband Elements Baseband refers to all technology elements in the phone design, which do not include RF functions.
NSD-5 3. System Module PAMS Technical Documentation Baseband-related External Interface For detailed information on interfaces to CCONT, CAFE, UI, and accessories, consult the CCONT, CAFE, and accessory modules in this chapter. FBUS FBUS (Fast Bus) is a serial interface between the DSP and data accessories and between the DSP and multipath analyzer. FBUS also is used as a data path during flash code downloading. This interface is a full-duplex, asynchronous, two-line bus.
NSD-5 3. System Module PAMS Technical Documentation Table 1 illustrates the signal characteristics of the interface. Also see the MAD4 Technical Specification (Reference 1) for decoding memory map and chip selects. Figure 4: Memory interface Signal Level (V) Low MEMAD(21:0) < 0.62 > 2.24 MCU/DSP address bus to external memory MEMDA(15:0) < 0.62 > 2.24 MCU/DSP bidirectional data bus to external memory MEMRDX < 0.62 > 2.24 Read strobe to external memory MEMWRX < 0.62 > 2.
NSD-5 3. System Module PAMS Technical Documentation Signal Level (V) Low EEPROMSCLK < 0.62 High > 2.24 Functional description EEPROM serial data clock Table 1: Electrical characteristics of the external memory interface Functional Timing Parameters Memory access timing is treated asynchronously. There are two reasons for this type of access. First, the external memories are inherently asynchronous. Second, two separate processors running at different frequencies share the memories.
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NSD-5 3. System Module PAMS Technical Documentation MAD4/RF Interface MAD4/RF Synthesizer Interface Figure 7: RF/MAD synthesizer interface Functional Description Figure 7 defines the MAD4/RF synthesizer interface. The synthesizer interface is capable of programming National LMX2330L Dual PLL Frequency Synthesizer. See Figure 8 and Reference 1 for synthesizer timing information such as set-up and hold time.
NSD-5 3. System Module PAMS Technical Documentation SYN_CLK 19.2000 MHz clock sent from MAD pin E16 (mdRFSClk) to synthesizer. The rising edge of the clock is used to clock data into the synthesizer. High Low Reset/Inactive Current Filtering Vdd - 0.6V 0 - 0.5V Low/low > 50 ns 1 mA max None SYN_LE1 Loading enable signal from MAD pin F16 (mdRFSLE1) to RF for the dual synthesizer. See data sheet of the synthesizer for details. High Low Reset/Inactive Current Filtering Vdd - 0.6V 0 - 0.
NSD-5 3. System Module PAMS Technical Documentation MAD4/RF Receiver and Transmitter Interface Figure 9: MAD/RF TX/RX interface Functional Description Figure 9 shows the interface between MAD4 and RF receiver and transmitter. It includes transmitter enable/disable, and RF power controlling. Some of the control signals have 2.8 CMOS level, while others have a PDM signal, which can be used to control RF behavior. The MAD4 PDM output is 2.8 V CMOS digital signal with pulse duration modulated with 9.
NSD-5 3. System Module PAMS Technical Documentation lular PA section and switch regulator providing cellular PA driver. PA is activated discontinuously in CDMA mode. High Low Polarity Rising time Filtering Vdd - 0.6V 0 - 0.5V High: TX on Low: TX off < 25 ns (10% - 90%_) BB: RC = 1.0 x 10-5 sec TX_LIM Signal from RF transmitter to MAD4 pin E15 (rfTxLim) to indicate maximum allowed output power is being exceeded, therefore to dynamically adjust the maximum commanded transmitter gain in CDMA mode.
NSD-5 3. System Module PAMS Technical Documentation RX_IF_AGC Signal from MAD4 pin A16 (mdRxIfAgc) to RIF pin AGC to control the gain of the receive IF section. It is activated only by CDMA. Type Range Resolution Load impedance Filtering PDM 0 - 2.8V 8bits @ 9.6 MHz clock Min: 10k BB: RC = 1.
NSD-5 3. System Module PAMS Technical Documentation . Figure 10: CAFE module block diagram Detailed Module Description CDMA Mode When the phone is in CDMA mode, I and Q components of the received IF signals from RIF are differentially AC coupled to CAFE ASIC. The input signal levels, impedance, and capacitance are described in Reference 3. For more information, refer to that document.
PAMS Technical Documentation NSD-5 3. System Module nent, RXI, is RXD[11..8]. For load impedance and input/output rise/fall time and other electric characteristics, refer to Reference 3 [CAFE application]. The transmitted signal is fed to the CAFE ASIC through data bus TXD[7:0] from MAD4 ASIC. The digital signal is registered inside CAFE ASIC. In-phase and quadrature components are separated from each other by using IQSEL from MAD4, and are D/A converted to analog signals.
NSD-5 3. System Module PAMS Technical Documentation Figure 11: MAD/CAFE interface diagram General Description As shown in Figure 11, the interface between MAD4 and CAFE consists of a parallel transmit bus (TxD), parallel receive bus (RxD) data, two serial data paths for both CAFE control and CODEC audio transmit/receive data, and an 8 kHz frame sync for the serial data bus. The interface also includes the system clock and other required clocks. CAFE provides MAD4 19.
NSD-5 3. System Module PAMS Technical Documentation Signal Parameter Min Typical Max Function “1” (V) “0” (V) Tf (ns) Tr (ns) 2.24 0 TBD TBD 2.70 0.30 Vbb 0.62 TBD TBD 8 kHz frame sync clock from MAD to CAFE to synchronize CAFE serial interface to MAD “1” (V) “0” (V) TIQSU (ns) 2.24 0 20 2.70 0.30 Vbb 0.62 “1” (V) “0” (V) TTXGON TTXGOFF TTXGS (ns) TTXGH (ns) 2.24 0 10 us 10 us 10 10 2.70 0.30 Vbb 0.62 “1” (V) “0” (V) TDH (ns) TDSU (ns) 2.24 0 20 20 2.70 0.30 Vbb 0.
NSD-5 3. System Module PAMS Technical Documentation CAFE/MAD4 Serial Data Interface MAD/CAFE serial data interface allows both DSP and MCU processors within MAD4 to read/write CAFE control registers. It also provides a serial interface with MAD4 for the CODEC to receive and transmit audio data. The serial data is transferred at a 320KHz data rate.
PAMS Technical Documentation NSD-5 3. System Module Figure 12: MAD/CAFE clock correlation/synchronization CAFE/RF Interface Figure 13: RF/CAFE interface General Description As shown in Figure 13, the interface between the RF parts and CAFE has the following signals (Table 4).
NSD-5 3. System Module Signal Parameter CLK19M22 Freq (MHz) PAMS Technical Documentation Min Typ Max 19.2 +/- 2.5 ppm Phase Noise (dBc/Hz) 10Hz -70 100Hz 1000Hz -110 -130 Settling Time Description 19.2MHz system clock input from VCTCXO to clock squaring circuit 5ms TX_IP Level (Vpp) Noise (uVrms) 0.97 1.0 1.03 <450 CDMA TX filter I channel differential output to TIF I/Q modulator input TX_IN Level (Vpp) Noise (uVrms) 0.97 1.0 1.
NSD-5 3. System Module PAMS Technical Documentation For I and Q channels Symbol Max differential input voltage range in stopband VIsb Input impedance ZIN Min 10 Typ 13 Max Unit 1 Vpp 16 kΩ Table 5: RXI, RXQ receive channel characteristics RF/CAFE CDMA TX Interfaces The digital transmit channel consists of two equal branches (TXI, TXQ). Each branch has differential output and the output signal is AC coupled. Table 6 lists some of the transmit channel characteristics.
NSD-5 3. System Module PAMS Technical Documentation function power management ASIC which has seven 2.8V linear regulators for the RF section of the phone. One 2.8V regulator is used to power up the baseband of the phone. Additionally, one adjustable regulator can be used to power up certain parts of the baseband. There also is a 5V charge pump, 5V regulator, and 3/5V regulator.
NSD-5 3. System Module PAMS Technical Documentation Noise level (nVrms/℘Hz) Max current (mA) Min Typ Max XMIS bias voltage 200 10 2.67 2.80 2.85 RFReg(1) Receiver 200 80 2.67 2.80 2.85 VR3 RFReg(0) Synthesizer 200 50 2.67 2.80 2.85 VR4 (CAFE_TX_GATE AND BAND_SEL) OR RFReg(3) Transceiver 200 80 2.67 2.80 2.85 VR5 /BAND_SEL OR RFReg(4) TX power detection 200 80 2.67 2.80 2.85 VR6 RFReg(5) CAFE 200 80 2.67 2.80 2.85 VBB Always on Baseband 200 125 2.
NSD-5 3. System Module PAMS Technical Documentation 4. Power Up With RTC Each of four methods is described in general in the following sections. When the battery is connected to phone, nothing will happen until the power–up procedure is initiated; for instance, by pressing the power button or by connecting a charger. After that the 32kHz crystal oscillator of CCONT is started (can take up to 1 sec), and the default regulators are powered up.
PAMS Technical Documentation NSD-5 3. System Module Power Up by Power Button t1< 1 ms t211 - 6 ms, VCXO settled t3: 62 ms, PURX delay generated by CCONT (*)VR1 VR6 and Vref might be later than VBB Figure 15: Timing of power-up sequence by power button After PWR–key has been pushed, CCONT sends PURX reset to MAD4 and turns on VR1, VBB, and VR6 regulators (if battery voltage has exceeded 3.0 V). VR1 supplies VCTCXO, VBB supplies MAD, and VR6 supplies CAFE.
NSD-5 3. System Module PAMS Technical Documentation Power Up When Charger Connected Figure 16: Timing of power-up sequency by a charger The power-up procedure is similar to the process described in the previous section, with the exception that the rising edge of VCHAR triggers the power up in CCONT. CCONT sets output CCONT_INT, MAD4 detects the interrupt and reads CCONT status register to find the reason for the interrupt (charger in this case).
NSD-5 3. System Module PAMS Technical Documentation Power Up by IBI IBI can power CCONT up by setting BTEMP to logical “1”. The recommended pulse width of the pulse is longer than 10 msec. After that, BTEMP acts as normal A/D input. Otherwise, the power-up procedure is the same as with the charger. Power Up With RTC RTC can power up the phone by setting the CCONT internal signal RTCPwr to logical “1” Otherwise, the power-up procedure is the same as with the charger.
NSD-5 3. System Module PAMS Technical Documentation With 2–wire charging, the charger provides constant output current, and the charging is controlled by the PWMOUT signal from CCONT to CHAPS. PWMOUT signal frequency is 1 Hz, and the charging switch in CHAPS is pulsed on and off at this frequency. The pulse width of PWMOUT is controlled through the serial data bus. There is a protection mechanism in CHAPS to protect the phone from over-charging the phone’s voltage.
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NSD-5 3. System Module PAMS Technical Documentation User Interface Functional Description As shown in Figure 18, the MAD4 serial interface is used to control the serial LCD on the user interface (UI) board and also to provide access to CCONT’s registers. The DataSelX and DataClk are generated by MAD4 during both transmit and receive cycles. Each device has its own chip select signal and must hold its data pin in a high-impedance state if its chip select is not active.
NSD-5 3. System Module PAMS Technical Documentation Signal To Signal Level (V) High Low Rising time Falling time Function UIF_CCONT_SCLK LCD/CCONT > 2.24 < 0.62 10 ns 10 ns serial port clock UIF_CCONT_SDIO LCD/CCONT > 2.24 < 0.62 10 ns 10 ns serial data CCONTCSX CCONT > 2.24 < 0.62 16 ns 16 ns chip-select to the CCONT serial device (a) RC filters with time constant = 100 ns used on these signals for ESD protection.
NSD-5 3. System Module PAMS Technical Documentation Parameters Definition Minimum Maximum Unit Tsdis Data in setup to rising edge 10 ns Tsdih Data in hold from rising edge 10 ns Table 10: Serial port timing System/Accessory Interface Description External accessory interface specifies a connector and set of signals that allow the phone to be used with a variety of standard peripherals (See Figure 21 following).
PAMS Technical Documentation VIN Charging input L_GND Charging ground NSD-5 3. System Module IR Interface If the phone supports internal infrared connection, the phone is set manually to infrared mode, via the user interface SW selection. This is the only way to configure the phone for the infrared mode. The infrared connection is always a point-to-point connection. Once the infrared mode is selected, the phone begins to operate via the infrared connection using the IrDA protocol.
NSD-5 3. System Module PAMS Technical Documentation microphone or the external microphone. When the PPH1 is used, the MCU software ignores the interrupt from HOOKINT since the PPH1 uses the TALK key on the phone to answer/end a call. Table 11 describes the detection for the audio accessories. For more detailed information, refer to Reference 7. AUXOUT = “1.
PAMS Technical Documentation NSD-5 3. System Module Figure 22: The interface between battery and transceiver (|) BTEMP Connections, IBI Accessories All accessories that can be connected between the transceiver and the battery or that itself contain the battery are called IBI accessories. Either the phone or the IBI accessory can turn the other on, but both possibilities are not allowed in the same accessory. IBI accessory can power on the phone by pulling the BTEMP line up to 3V for at least 10ms.
NSD-5 3. System Module PAMS Technical Documentation Figure 23: The interface between battery and transceiver (||) RF Module Overview The RF Module is compliant with the requirements of J-STD-018. Constructed on a sixlayer PCB that is 1.0mm thick, the dielectric separating the layers is RCCu. All other dielectrics measure FR4. Environmental Specifications The ambient temperature range is from -30oC to +85oC. Vibration and Free Fall Specifications are listed in the NMP Standard Product Requirements.
NSD-5 3. System Module PAMS Technical Documentation Maximum Ratings The maximum battery voltage during the transmission should not exceed 4.5V. Higher battery voltages may destroy the power amplifier and other circuitry. The minimum battery voltage is 3.2V. RF Connector If nothing is plugged into the phone, the RF is connected to the single band antenna. When the RF connection is made, the RF path is switched mechanically from the antenna to the cable plugged in.
NSD-5 3. System Module PAMS Technical Documentation bias. Since a voltage of greater than 3.8V was required for the bias, the 5-volt output from CCONT has been utilized. The collectors of both stages of the PA are based from the battery source. The reference current provided by the current source (formed by V601 and V602) controls gain of PA module by means of the Iref pin. The Tx-Gate signal is used to switch a current mirror to switch the PA with approximately 4 mA current.
NSD-5 3. System Module PAMS Technical Documentation . Receiver The following sections describe the Rx section chain from duplexer down to the I/Q signals for CDMA fed to the baseband. Front End In DCT3, the Stealth LNA and downconverter was used with an external bipolar LNA. In Zim, the Alfred front end (N701) is used (same as that of Columbia). The 800MHz section of Alfred IC is unused. It is critical that the LO must be present 5ms before Alfred is powered on. The software has been informed about this.
NSD-5 3. System Module PAMS Technical Documentation Min LO drive -7dBm Max LO drive -3dBm Gain =16dB NF =4dB IIP3 2dBm Current =13mA Table 15: PCS 1900MHz Downconverter Specs Interstage SAW Filter The Rx interstage filter used is Z702. Insertion loss = 4.1dB. Attenuation DC - 1700MHz = 20dB 1850MHz - 1910MHz = 15dB 2058MHz - 2118MHz = 15dB 2186MHz - 2246MHz = 22dB 2246MHz - 6000MHz = 10dB IF SAW Filter The IF SAW filter used is Z703. Key Parameters Center frequency 128.
PAMS Technical Documentation NSD-5 3. System Module CDMA AGC The RIF IC contains a wide dynamic range AGC circuit for CDMA. The AGC provides +42.5 to -42.5dB of gain controlled by the PDM line RX_IF_AGC. IQ Demodulator The IQ demodulator mixes the 128.1MHz IF signal down to DC with two mixers, one at quadrature to the other. The LO is at 256.2MHz and is divided by two in the demodulator.
NSD-5 3. System Module PAMS Technical Documentation the baseband for Tx out-of-lock detection. 2nd Rx VHF LO Synthesizer This submodule contains a VHF VCO, a loop filter, and a single synthesizer. This synthesizer is only tuned to a single frequency. The LO converts the received signal to baseband data. This submodule will use a mask programmable synthesizer (Fujitsu). System Reference Oscillator (VCTCXO) This submodule is the reference clock for the engine.
PAMS Technical Documentation NSD-5 3. System Module Figure 25: Block diagram of basic phase locked loop The LMX2330L of monolithic, integrated, dual frequency synthesizers, including prescalers, is to be used as a local oscillator for RF and first IF of a dual conversion transceiver. In this explanation of LMX2330L IC, RF means the frequency range of the TX/RX UHF and IF is the frequency range of the TX-VHF. The LMX2330L contains dual modulus prescalers.
NSD-5 3. System Module PAMS Technical Documentation Control Bits DATA Location C1 C2 0 0 IF R Counter 0 1 RF R Counter 1 0 IF N Counter 1 1 RF N Counter Table 16: Control bits vs data location Divide Ratio R 15 R 14 R 13 R 12 R 11 R 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . . . . . . . . . . . .
NSD-5 3. System Module PAMS Technical Documentation 7-Bit Swallow Counter Divide Ratio (A Counter) RF Divide Ratio A R 7 R 6 R 5 R 4 R 3 R 2 R 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 . . . . . . . . 127 1 1 1 1 1 1 1 Divide Ratio A R 7 R 6 R 5 R 4 R 3 R 2 R 1 0 X X X 0 0 0 0 1 X X X 0 0 0 1 . . . . . . . .
NSD-5 3. System Module PAMS Technical Documentation fOSC: Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767) P: Preset modulus of dual modulus prescaler (for IF: P=8 or 16; for RF: P = 32 or 64) N= (Px B)+A Programmable Modes Several modes of operation can be programmed with bits R16-R20, including the phase detector polarity, charge pump TRI-STATE, and the output of the Fo LD pin.
PAMS Technical Documentation NSD-5 3. System Module Figure 26: The polarity of VCO Serial Data Input Timing Data in parentheses indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first.
NSD-5 3. System Module PAMS Technical Documentation Phase Comparator and Internal Charge Pump Characteristics Phase difference detection range: -2 ≠ to +2 ≠ The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked.
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NSD-5 3. System Module PAMS Technical Documentation Signal Name From/ Control To Parameter TX_LIM TIF MAD TX_RF_ AGC MAD TX IC Min Typ Max Unit Function Tx higher than set on TX_LIM_ADJ 0 V TX_LIM_ADJ and RF power detector comparator output read by MAD Tx lower than set on TX_LIM_ADJ 2.7 v PDM voltage max gain 0 v PDM voltage min gain 2.
NSD-5 3. System Module PAMS Technical Documentation RF Regulators Regulators CCONT, CHAPS Comments VR1 Synth block - VCTCXO supply no change VR2 Rx block Alfred. Needs to be switch on 5 ms (minimum delay) after PLL (UHF-RX) programming. Turn off sequence for VR2 and VR3 remains same. RIF moved from VR3 to VR2. default set to nonslotted mode upon phone power-up VR3 Rx block: RX VHF Synth block: PLL, UHF VCO VR4 Tx block: TX RFA (discrete) and attenauator Puncturing should remain the same.
NSD-5 3. System Module PAMS Technical Documentation Reference 1. MAD4 V3 Technical Specification, DAS00491-EN, bulletinboard/approved/hd983/nhdx/mad4/dsgn_spc/MAD4_v3_tech_spec_2.2 2. DCT3 MAD4 Resource Manager Specification and implementation, DAS00212-EN, bulletinboard/hd980/controlled_docs/e1/asics/mad4/mad4_common/design/ resc_mgr_spec 3. CAFE ASIC Specification, DAS00153-EN, /bulletinboard/hd980/controlled_docs/e2/asics/cafe/design/cafe_spec_1.5 4. Power distribution doc 5.
