User Guide

PAMS Technical Documentation 10. Troubleshooting
NSD-5
Issue 1 05/02 Nokia Corporation Page 7
detection). These readings can be accessed through the service software. Check for
shorts or opens on the resistor networks connected to these signals if the flash align test
software reports that they are out of range.
Watchdog
CCONT’s watchdog circuitry consists of an 8-bit down counter that causes CCONT to
power down when zero is reached. The counter may be reset by loading a new, non–zero
value into the watchdog register via CCONT’s serial bus. It is difficult to verify the watch-
dog function, but the serial bus may be verified.
There is a watchdog disable pin, which allows the watchdog timer to expire without
shutting down the phone. This pin is mainly used as one of the methods to turn on
CCONT from power off mode. While the phone’s power key is pressed, this pin should be
pulled low and can be checked at TPD 26 using a 70k resister. The watchdog can be dis-
abled by pulling down the above-mentioned pin (WD_DIS) by shorting TPD 26 and
ground.
Serial bus
Since the serial bus is used to control almost all of CCONT’s functions, any shorts or open
circuits on these three lines would cause CCONT to be completely nonfunctional. The
main symptoms are the following:
CCONT will turn on when the power key is pressed (verify this by checking Vbb), but will
then power off after 32 seconds. All three serial bus signals (CCONTCSX,
UIF_CCONT_SDIO, and UIF_CCONT_SCLK) should toggle when attempting to write to a
CCONT register.
Note: If the LCD does not come on during this time, it may indicate that the serial bus is functional,
but the phone does not have valid flash code.
Clocks
Sleep Clock
The 32kHz sleep clock is generated by CCONT, and can be checked at TPD32. The 32kHz
square wave will be present only after the phone is turned on.
System Clock
The 19.2MHz system clock is generated by the VCTXO in the RF section, and then squared
in CAFE. Check TPD11, which should be a 2.8V squarewave. This clock is not active during
the phone’s sleep mode (CLK_EN is low during sleep mode).
CDMA Clock
The CDMA clock is 9.8MHz and is generated in CAFE with a PLL. This should be a 2.8V
squarewave and can be verified at TPD10.
Charging Circuit
The charging switch, CHAPS, is controlled by a PWM from CCONT. This PWM can be at