User Guide

3$067HFKQLFDO'RFXPHQWDWLRQ 6FKHPDWLFV/D\RXWV6(/Y 16:
,VVXH 1RNLD0RELOH3KRQHV 3DJH$
J162
J212
J141
J143 SLEEPCLK
J164
RXPWRI
J142
J255
J265
J130
J261
J131
J260
J262
J213
J140
J151
J150
J210
J211
J209
J208
J207
Test point description
Test
point
Name From–to Level Description
J121 PCMSCLK COBBA A4– MAD L4 8.0 kHz (digital), 8.1 kHz
(analog)
J140 PURX CCONT A5–MAD M1, D201
B4, COBBA D5
Reset state 0V, nor-
mal state 2.8V
RESET power up/down
J141 CCONTINT CCONT B7–MAD B10 Pulse active 2.8V,
non–active 0V
Charger interrupt
J142 RFCEN MAD J3– D201 A5, CCONT
G4
Pulse active 2.8V,
non–active 0V
Active state
J143 SLEEPCLK CCONT B8– MAD M2 Pulsed DC <
0.8V/>2.4V
32.768 kHz, power on
J150 WDDIS/PWRONX X101–CCONT E4 Pulse active 0V,
non–active 2.8V
Watchdog disable
J151 GND J156–GND Ground for WDDIS
J207 RAMSELX MAD M10– D200 B5
J208 ROM1SELX MAD N10– D201 D7
J209 COBBASIO MAD N4– COBBA B5 Bidirectional data line
J210 COBBACLK COBBA A2– MAD N2 Pulsed DC
(<0.5V/>2.15V)
COBBA system clock
J211 COBBADAX MAD N3– COBBA C3 Data ready flag
J212 DATASELX MAD J2– CCONT A7 Read/write enable
J213 RFCSETTLED MAD M5– COBBA C5 Pulse active 2.8V,
non–active 0 V
Active state
J262 COBBACSX MAD L5– COBBA A5 Chip select
J255 RFC EROTUS 25– COBBA B1 0.7 Vpp sinewave 19.44 MHz clock
J260 PCMRXDATA MAD N5– COBBA A7 Receive data line
J261 PCMTXDATA COBBA B4– MAD M4 Transmit data line
J265 PCMDCLK COBBA C4– MAD M3 1.08 MHz (digital), 1.215
MHz (analog)
Component Layout - Top