User Guide

Camera Module CCS Technical Documentation
Page 8 ¤Nokia Corporation Issue 2 11/02
Signals specifications
Signals and timing
The fast serial interface of digital image data is employed for the VGA camera module.
The fast serial interface described in this document is named CCP (Compact Camera
Port). In terms of signaling scheme, CCP is based on the idea of IEEE standard LVDS sig-
naling scheme (current mode differential low voltage signaling method). CCP described
in this document utilizes lower voltage than that of standard LVDS. The low voltage LVDS
is named in this document sub LVDS. CCP is an one-way differential serial camera con-
nection with clock and integrated line / frame synchronization:
Figure 2: CCP interface between camera and engine
D+ and D- are differential picture data output from the camera module. This data is
written on each falling edge of Clk. Data format is least significant bit first. When noth-
ing is being transferred, D remains high, except in power shut-down.
Clk+ and Clk- are differential pixel clock. Data should be read by the receiving end on
rising edge. When nothing is being transferred, Clk remains high, except in power shut-
down.
Synchronization
Each image line that is received begins with line synchronization code and ends with line
end code. Each frame begins with frame synchronization code and ends with frame end
code. At frame start and frame end no line synchronization are added but they are
replaced by the frame synchronization.
Sub LVDS specification
General
The fast serial transfer of image data from the camera module to Nokia engine is to be
achieved based on 1.8 power supply condition. Accordingly, modified LVDS type current
mode transmitters/receivers is used. In this document, the LVDS scheme which is modi-
fied corresponding to 1.8 V is named sub LVDS. The figure below shows simplified config-
uration of sub LVDS
D+
D-
Camera Engine
Clk+
Clk-