User Guide

NSW-5
System Module UT5U
PAMS Technical Documentation
A–12
Issue 1 10/00
 Nokia Mobile Phones Ltd.
Layout Diagram of UT5U v.17_4 2/2
Table 1. Test point description
Test
point
Name From–to Level Description
J150 WDDIS/PWRONX X101–CCONT E4 Pulse active 0V,
non–active 2.8V
Watchdog disable
J156 GND J156–GND Ground for WDDIS
J151 RFCEN MAD J3– D201 A5, CCONT
G4
Pulse active 2.8V,
non–active 0V
Active state
J152 PURX CCONT A5–MAD M1, D201
B4, COBBA D5
Reset state 0V,
normal state 2.8V
RESET power up/down
J153 CCONTINT CCONT B7–MAD B10 Pulse active 2.8V,
non–active 0V
Charger interrupt
J154 DATASELX MAD J2– CCONT A7 Read/write enable
J155 DATA_CLK CCONT A8– MAD J1
J157 SLEEPCLK CCONT B8– MAD M2 Pulsed DC <
0.8V/>2.4V
32.768 kHz, power on
J204 RAMSELX MAD M10– D200 B5
J205 ROM1SELX MAD N10– D201 D7
J206 COBBACSX MAD L5– COBBA A5 Chip select
J207 COBBASIO MAD N4– COBBA B5 Bidirectional data line
J208 COBBADAX MAD N3– COBBA C3 Data ready flag
J250 RFC EROTUS 25– COBBA B1 0.7 Vpp sinewave 19.44 MHz clock
J251 COBBACLK COBBA A2– MAD N2 Pulsed DC
(<0.5V/>2.15V)
COBBA system clock
J252 RFCSETTLED MAD M5– COBBA C5 Pulse active 2.8V,
non–active 0 V
Active state
J253 PCMRXDATA MAD N5– COBBA A7 Receive data line
J254 PCMTXDATA COBBA B4– MAD M4 Transmit data line
J255 PCMDCLK COBBA C4– MAD M3 1.08 MHz (digital), 1.215
MHz (analog)
J256 PCMSCLK COBBA A4– MAD L4 8.0 kHz (digital), 8.1 kHz
(analog)
J257 ADATA COBBA B2– MAD N1