User Guide
Nokia Customer Care Schematics / Layouts hl9_14 NHL-12
Issue 2 10/2004 Copyright © Nokia 2004. All rights reserved. Page 3
Bluetooth Circuit v.2.0, ed.71
Sheet of
VBC02_VREG_OUT
VOLTAGE REG OUTPUT
2.8V SUPPLY TO BC02
VBC02_CLK_BUFF
VBC02_RF_SWITCH
SUPPLY
PCM_IN
SPI(3:0)
NAME
5
REQUIRED ON PROJECT SPECFIC GENIO CONNECTION SHEET
G_LPRF(15:0)
G_LPRF[20]
G_LPRF[19]
BC02_UART(3:0)
BT_RESETX
BT_WAKEUP
UART_TX
PCM_CLK
PCM_IN
PCM_SYNC
G_LPRF
2
3
4
CONNECTION OF G_LPRF(23:0) AND VBC02 VOLTAGE SUPPLY NETS
6
UART_RTS_P
UART_RTS_P
PCM_OUT
NAME
RECOMMENDED
VBAT (MAS9161)
1.8V
2.8V or 1.8V
2.8v (WLAN / APE)
PCM_CLK
PCM_SYNC
13
VBC02_VREG_IN
VBC02_VIO
UART_CTS_P
UART_TX
UART_RX
VOLTAGE REG INPUT
BC02 I/O LEVEL
CLOCK BUFFER
WLAN RF SWITCH
G_LPRF(23:0)
G_LPRF[23]
7
LV_UART_RX
LV_UART_CTS_P
LV_UART_CTS_P
PCM_OUT
BT_RESETX
10
PURX
SPI_CLK
1
SYSCLK
SPI(3:0)
0
UART_CTS_P
UART_RX
HOST_WAKEUP
BT_WAKEUP
G_LPRF[22]
FIELD
G_LPRF[21]
G_LPRF[18]
G_LPRF[16]
G_LPRF[17]
UART_RTS_P
SPI_MISO
BC02_UART(3:0)
G_LPRF(15:0)
8
9
SPI_CSB
UART_TX
SPI_MOSI
CLK_ENABLE
WLAN_CTRL
WLAN_RF
CLK_ENABLE
WLAN_CTRL
WLAN_RF
11
12
HOST_WAKEUP
HOST_WAKEUP
Copyright (C) Nokia Corporation. All rights reserved.
DBMGR
THIS DRAWING IS PROTECTED BY COPYRIGHT AS AN UNPUBLISHED WORK.
UNAUTHORIZED REPRODUCTION OF THIS DRAWING IS NOT PERMITTED.
THIS DRAWING CONTAINS PROPRIETARY AND CONFIDENTIAL INFORMATION.
This document is property of Nokia Corporation
11
Yes
Print
Assoc
CSR BC02_ROM Bluetooth Circuit
Name
2.0
V.Drw.
BLUEBIRD P1501
Proj
13
12
GND
BTH_TEST
empty
BC02_UART(3:0)
SPI(3:0)
TESTCLK
UART(6:3)
$eng_rel_db/master/temp/hl9_09_hw/cbb/SYS/lprf
File
Appr
Des.
Dr.
5
4
3
0
19
9
17
6
C6031
2320778
10n
3
16
3
3
BC02_VIO
GND
GND
7
10
8
GND
2320778
10n
C6033
VOLTAGE_REGULATOR
decoupled_1u0
CTRL
MODE
VOUT
2u2
GND
22nH
3646239
L6034
VBC02_VREG_OUT
22
23
C6047
2316001
2
0
1
bluebird_ref_design
BTH_FILTER
ANT
BC02_VDD_ANA
BTH_A
BTH_B
CTRL
WLAN
2
C6045
2320540
15p
J2
VSS_ANA
J3
XTAL_OUT
VSS_ANA
J4
J5
AIO2
J6
VDD_MEM
K2
VSS_ANA
XTAL_IN
K3
VDD_ANA
K4
K6
VREG_IN
VDD_MEM
K7
K9
VDD_IO
H1
VDD_VCO
H10
PCM_CLK
LOOP_FILTER
H2
H4
AIO0
AIO1
H5
H6
VDD_MEM
H7
UART_RTS
H8
UART_CTS
H9
UART_RX
J10
UART_TX
E9
VSS_CORE
TX_A
F1
Host_WakeUp/PIO6
F10
F2
VSS_RADIO
F8
PIO5
PIO7
F9
VSS_VCO
G1
G10
PCM_SYNC
G2
VSS_VCO
PCM_OUT
G8
PCM_IN
G9
C9
SPI_CSB
RF_IN
D1
D10
VDD_IO
D2
VSS_RADIO
AUX_DAC
D3
RESETB
D8
TX_B
E1
VDD_CORE
E10
VSS_RADIO
E2
E3
PIO11
E8
BT_WakeUp/PIO4
B8
SPI_MISO
B9
VDD_RADIO
C1
C10
SPI_CLK
C2
VDD_RADIO
C3
PIO9
C4
PIO10
PIO8
C5
C6
TEST_EN
C7
RESET
C8
SPI_MOSI
N6030
VDD_IO
A3
A6
VDD_MEM
VDD_MEM
A7
VDD_MEM
A9
PIO0
B1
B2
PIO1
UART_RTS_P/PIO2
B3
B4
UART_CTS_P/PIO3
FLASH_EN
3
2
GND
0
J9,K10,A1,A2,D9,B5,B7,A10,B10,J7,F3=
4370975
BC213143A-17-RK-E4
GND
1430778
R6030
BC02_VIO
18
6
5
4
2320778
C6043
10k
0
2
10n
C6035
2320778
1
TX_MATCHING
calvin
BALUN_A
BALUN_B
BC02_TX_A
BC02_TX_B
BC02_VDD_ANA BC02_VDD_VCO
10n
1
BTH_ANT
calvin
ANT
11
ape_discrete_2v8
CLOCK_BUFFER
CLK_OUT
ENABLE
SYSCLK
TESTCLK
GND
GND
2R2
20
GND
21
GND
GND
1430691
R6034
RFCONVCTRL(2:0)
AUDUEMCTRL(3:0)
GENIO(31:0)
LPRFCLK
PUSL(3:0)
G_LPRF(23:0)
UART(6:3)
SPI(3:0)
BC02_UART(3:0)