User Guide

CCS Technical Documentation System Module
NPM-2NX
Issue 1 07/02 ãNokia Corporation Page 41
MEMORY Block Interfaces
Table 15: Memory interface signals
Rip
#
Signal
Name
DAMPS
/
GSM19
00
Connected
from-- to
I/O
Signal Properties
A/D--Levels---Freq./
Timing resolution
Description / Notes
MEMADDA(23:0) External Memory Addr/Data Bus
0-15 EXTADD
A 0:15
Mem-
ory
UPP In/
Ou
Dig 0/1.8 V 25 / 150
ns
Burst Flash Address (0:15) & Data
(0:15)
Direct Mode Address (0:7)
16-
23
EXTAD
16:23
Mem-
ory
UPP In Dig 0/1.8 V 25 / 150
ns
Burst Flash Address (16:23)
Direct Mode Data (8:15)
MEMCONT(8:0) External Memory Control Bus
0 ExtWrX Mem-
ory
_WE
UPP In Dig 0/1.8 V Write Strobe
1 ExtRdX Mem-
ory _OE
UPP In Read Strobe
2
3 (FlsBAA
X)
VPPC-
TRL
Mem-
ory
(VPP)
UPP In VPP=1.8V,=> VIO used internally
for VPP
VPP=5/12V, VPP used
4 FlsPS Mem-
ory PS
UPP In/
Ou
t
25 ns Burst Mode Flash Data Invert
Direct Mode Address (17)
5 FlsAVD
X
Mem-
ory
_AVD
UPP In Flash Addr Data Valid/ Latch
Burst Addr
Direct Mode Address (18)
6 FlsCLK Mem-
ory CLK
UPP In 50 MHz Burst Mode Flash Clock
Direct Mode Address (19)
7 FlsCSX Mem-
ory _CE
UPP In Flash Chip Select
8 FlsRDY Mem-
ory RDY
UPP Ou
t
Ready Signal for Flash
9 FlsRSTX Mem-
ory _RP
UPP Ou
t
Flash reset, 0 active, (FLSRPX)
GENIO(28:0) General I/O Pin used for extra control
23 FLSWR
PX
Mem-
ory
_WP
UPP Ou
t
Dig 0/1.8 V O Write Protect, 0-active protected
Globals Power supplies and production test pad