User Guide

NPM-2NX
System Module CCS Technical Documentation
Page 38 ãNokia Corporation Issue 1 07/02
Table 13: UPP GENIOs (may be described in other tables as well)
5 FlsAVD
X
UPP Mem-
ory
O
ut
Di
g
0-1.8 V Flash Addr Data Valid/ Latch Burst
Addr
Direct Mode Address (18)
6 FlsClk UPP Mem-
ory
O
ut
Di
g
0-1.8 V 50 MHz Burst Mode Flash Clock
Direct Mode Address (19)
7 FlsCSX UPP Mem-
ory
O
ut
Di
g
0-1.8 V Flash Chip Select
8 FlsRDY UPP Mem-
ory
In Di
g
0-1.8 V Ready Signal for Flash
9 FlsRSTX UPP Mem-
ory
In Di
g
0-1.8 V Reset Signal for Flash
GENIO(28:0) Memory Write Protect from GENIO bus
23 GENIO(
23)
UPP Mem-
ory
O
ut
Di
g
0-1.8 V Write Protect, 0-active
Ri
p
#
Signal
Name
DAMPS,
GSM19
00
Connected
from--- to
UPP
I/O
Signal Properties
A/D--Levels---Freq./
Timing resolution
Description / Notes
GENIO(28:0) General I/O Pins, The bold font lines are only valid one for product.
0 Secu-
rity
bypass
UPP In Dig 0-1.8 V In / Pull Up R&D only
1 EmuP-
resent
UPP In Dig 0-1.8 V In / Pull Up R&D only
2 Not
Used
UPP In/
Out
Dig 0-1.8 V In / Pull Up
3 Not
Used
UPP In/
Out
Dig 0-1.8 V In / Pull
Down
4 LCDRstX UPP Dis-
play
Out Dig 0-1.8 V Out / 0 Display Reset
5 Not
Used
UPP Out Dig 0-1.8 V In / Pull
Down
6 Not
Used
UPP Out Dig 0-1.8 V In / Pull
Down
7 Not
Used
UPP Out Dig 0-1.8 V In / Pull
Down
8 TX_enab
le
UPP RF Out Dig 0-1.8 V Out / 0 TX power enable