User Guide

RH-20 Company confidential

System Module and User Interface CCS Technical Documentation

Page 36 Nokia Corporation. Issue 1 10/2003

Memory Block

For the MCU UPP includes ROM, 8 kbytes, that is used mainly for boot code of MCU. To

speed up the MCU operation small 4 kbyte cache is also integrated as a part of the MCU

memory interface. For program memory 8Mbit (512 x 16bit) PDRAM is integrated. RAM

block can also be used as data memory and it is byte addressable. RAM is mainly for MCU

purposes but also DSP has also access to it if needed.

In addition to UPP integrated RAM RH-20 baseband has also UPP external SRAM. This is

implemented in combo memory (single package with stacked ICs, 128Mbit flash + 8 Mbit

SRAM).

MCU code is stored into external flash memory. Size of the flash is 128Mbit (8192 x

16bit) The HDi 13 baseband supports a burst mode flash with multiplexed address/data

bus. Access to the flash memory is performed as 16–bit access. The flash has Read While

Write capabilities which makes the emulation of EEPROM within the flash easy.

Security

The phone flash program and IMEI codes are software protected using an external secu-

rity device that is connected between the phone and a PC.

Clock distribution

Figure 16: Clock Distribution Diagram

UPP

CTSI

UEM

VCTCXO

26MHz

HELGA

PLL

MCU

DSP

SLICER

VR3

26 MHz

32 kHz

SLEEPX

32 kHz

RFBUSCLK 13MHz

CBUSCLK 1MHz

DBUSCLK 13MHz

LCDCLK max. 6.5MHz

SIMCLK max. 3.25MHz

HELGO